Global Sources
EE Times-India
EE Times-India > EDA/IP

Synopsys preps for 'techonomic' challenges

Posted: 01 Jul 2008     Print Version  Bookmark and Share

Keywords:EDA industry  "techonomic"  technology  money 

de Geus: There's a trade-off between innovation, execution and collaboration. You can execute, but if you don't collaborate with the right people, you have nothing.

The strategy of EDA company Synopsys Inc. is based on offering complete design systems. That involves drilling down to detail the semiconductor physics while reaching up to embrace system complexity.

Seeing where the industry is going is relatively easy. According to chairman and CEO of Synopsys Aart de Geus, the difficult bit is laying out an EDA offering at the right time, when customers are ready to take it up. And right now, everything in the EDA space has to be rethought, according to the executive.

Since co-founding Synopsys in 1986, de Geus has expanded the company from a synthesis start-up to a Rs.4,802.53 crore ($1.2 billion) per annum vendor of design software, IP and professional services for the chip industry. Here's how he sees the EDA industry today, and how he he'll continue to lead Synopsys to growth.

What are the biggest challenges for the EDA industry?
I call the challenges "techonomic" because technology and money affect each other. Technologically, some problems stem from physics moving up, and other problems stem from function moving down. In physics, the single biggest challenge and opportunity is power in its various meanings. Low power is becoming an essential challenge for mankind. What started in portable devices is now going into all electronic products. We have to tackle many issues, from dissipation of heat to green electronics.

A few years ago, it became almost impossible to make the microprocessors run faster easily. As you grew the speed, the power consumption went completely non-linear. The result has been radical and phenomenal shift in architecture to multi-core, which is the direction where the entire world of sophisticated chips is now going. In multi-core, you're still getting more output but substantially lower power. Today, it's almost down to the question of how much energy it takes to switch a state or store a state. Among other things, a lot of leakage and dynamic heat are produced. And you have the issue of battery life.

Green technology will also help power to be a key driver for a few years, and this is why we have a low-power methodology. To optimise power use, we have to use intelligent control systems. The amount of electronics that will be created to manage power better will be huge, as in hybrid cars for example. Venture capital investments are growing in power management, power optimisation and power reduction. Power, which was initially a breakdown, is becoming a breakthrough. Anywhere you look the key is power.

The other big topic is verification and validation. The complexity of today's interrelated, heterogeneous systems is going much more rapidly than Moore's Law, not only in transistors, but also in embedded software. Well over 65 per cent of the engineering time goes into various forms of verification and validation. It is just going to grow now.

The third challenge for EDA relates to collaboration. Synopsys spends 30 per cent of revenues on R&D, and that's even not close to sufficient. I would like to have another 2,000 R&D engineers today. Just give me the opportunity. To achieve that, we'll collaborate more with our customers, leverage their R&D capabilities and help them leverage their own efficiencies.

Everything has to be rethought, but collaboration fundamentally changes the relationship. For example, last year we announced that Intel has agreed on a multi-year collaboration with Synopsys. We have collaborated with Intel Israel in a very strategic project. Last year, Renesas moved to Synopsys and we collaborate with them.

Fourth, there's a trade-off between innovation, execution and collaboration. You can execute, but if you don't collaborate with the right people, you have nothing. And then you have to go back to innovation. Today, we're at the collaboration phase—working together, competition or consolidation, which is a forceful way of collaboration. There's an enormous change in the collaboration dimension.

On top of that, it is amazing how financial stresses drive the high-tech economy, both in creating challenges and new markets. It forces companies to do more with less, and creates opportunities to solve new problems.

Software is becoming both a bottleneck and a differentiating factor in design. How do the industry and Synopsys tackle this?
I strongly agree with your point. The growth of software has been faster than hardware and today, semiconductor companies are hiring more software engineers than hardware engineers. This brings great opportunities and huge challenges. Thinking that "software is great, because it's easy to change" is a recipe for disaster, When people make little changes and before you know it, everything becomes very difficult to verify.

Very complex systems need enormous amount of prototyping and verification. For years, we have invested in the system side alongside the software side, also with reusable IP blocks, which have hardware, verification software and some of the embedded stacks. Our products allow modelling of the hardware, so that software could be exercised over it. One of the reasons I am excited about Synplicity is that they have pioneered a rapid prototyping product that allows taking chip designs and mapping them into an FGPA, which can be used to run embedded software. Synplicity is interesting because they have a business of Rs.120 crore ($30 million) plus, so the critical mass will help us very quickly become the largest EDA player in tools for the system side.

How can the EDA industry help companies minimise design and manufacturing costs?
The biggest cost for consumer goods is manufacturing, in terms of engineering time and tools. Investing in tools, methodologies and people that minimise chips is actually the number one objective for cost, and EDA helps achieve that. Design costs are a function of size, technology and yield. Tools like ours help shrink designs by 5-7 per cent. Those tools are not free, but the impact on the design cost and the manufacturing cost can be huge.

What's your strategy for growth?
The EDA industry has challenges in regard to growth rates, but Synopsys had a double-digit growth for the last four years. Complexity drives companies with improper EDA tools into big difficulties. The glued-together "best-in-class tools" give worst-in-class results. Speed, power, signal integrity and yield are all interrelated. If you just glue together solutions, one tool will do great and will cause big problems for the next tool.

Over the last 10 years, our strategy has included five steps. First, we try to have truly best-in-class tools wherever we can. I don't want to say that we're best-in-class everywhere, but in many places.

Second step is to have a complete solution. We acquired Avant to have better place and route; we invested in IP, and we acquired companies and invested in DFM. This year, we'll finally fill the last big hole, which is analogue custom implementation, which was the one place where Cadence had a unique position.

Third step is integration of the tools so that they work together really well. Tools have to be able to know what's going to happen later, so that one tool doesn't do stupid things here, and another tool will have problems there. For example, our synthesiser is now capable of predicting if a layout will have congestion and change the netlist so that the place and route will be less congested.

The fourth step is to route the system down to the physics. We're in an age when physics is back. Our job is to protect the designer from all the difficult physics. Physics expresses itself in areas such as particles, vias, materials and lithography. This is the reason we invested substantially in design for manufacturing. We have people working on 22nm right now.

The fifth step is to reach up to systems. As chips become more complex, we will be able to build more things by IP reuse and software on top of that, and that's an area where we can see expansion.

All these issues stress the need to predict the future, which for me, it is not so hard—but it is always difficult to predict the timing. Sometimes the reason why something takes off is not knowable, but the "techonomic" moment has to be right.

- Amir Ben-Artzi

EE Times

Comment on "Synopsys preps for 'techonomic' chal..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top