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How to port a monitor/LCD application from a ST727x4 to a ST7FLCD1 device

Posted: 30 Nov 2004     Print Version  Bookmark and Share

Keywords:embedded 

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

18 September 2002 Revision 1.1 STMicroelectronics Confidential 1/16

By DTV - Monitor MCU Applications Lab

AN1581

Application Note

How to Port a Monitor/LCD Application

from an ST727x4 to an ST7FLCD1 Device

.

Introduction

This application note provides all the technical details, regarding both hardware and software sides,

to port an existing monitor application, running on ST727x4 Monitor MCU family, to the ST7FLCD1

Monitor MCU. It is meant to make the porting job simpler and faster.

This application note will describe all the differences between the ST72T774 60K OTP MCU (the

most commonly used MCU for early development) and the ST7FLCD1 MCU. As such, only the

relevant parts will be quoted from each respective MCU datasheet.

Note: This application note does not replace the full MCU specification document which is still needed as

a reference. Differences exist among the ST727x4 family, so please refer to the corresponding

datasheet for any other MCU of the ST727x4 family.

1 Overall Differences

The main differences regarding the features of each MCU are detailed below:

Feature ST72T774 ST7FLCD1

RAM 1 Kbyte (928 bytes exactly) Full 2 Kbytes (2,048 bytes)

Dedicated EDID DMA Area

for DDC2B

No (anywhere in Memory Map)

2 x 256 Bytes in RAM

Can be re-used as usual if either DDC2B

cell is disabled

Stack 256 Bytes maximum

Program Memory 60 Kbytes, OTP Type

60 Kbytes, FLASH Type

3 sectors: 4 Kbytes / 4 Kbytes / 52 Kbytes

Internal Frequency 8MHz typical, 9MHz maximum

Low Power Modes

WAIT

No HALT (generates a reset if fetched)

WAIT

HALT (if watchdog disabled)

Watchdog Software programmable

Software programmable

Lock-up Protection

Additional Protections

Illegal OpCode (triggers reset)

Illegal Address (triggers reset)

Illegal OpCode (triggers reset)

Free R/W Access anywhere

Operating Supply 4.0 V to 5.5 V 4.5 V to 5.5 V

Package CSDIP42, PSDIP42 or TQFP44 SO28

Overall Differences AN1581

2/16 STMicroelectronics Confidential

Cell ST72T774 ST7FLCD1

Sync Processor Yes No

USB Yes No

TMU Yes No

I2

C Single Master

Normal/Fast Modes

Yes

Speed up to 400 kHz (Standard/Fast)

Yes

Speed up to 400 kHz (Standard/Fast) and

up to 800 kHz at user's risk

DDC

DDC1 / DDC2B / P&D / FPDI-2 with End of

Download Flag

DDC with fixed E-DDC address and 1

programmable address decoding

2 x DDC2B with End of Download and End

of Communication Flags

2 x DDC with fixed DDC/CI address and 2

programmable addresses decoding for each

cell

External Interrupts 2 (falling edge) 2 (edge programmable)

Timer

1 with 2x Input Capture, 2x Output Compare

and PWM capabilities

1 with Programmable Prescaler, Autoreload

and Buzzer Output

1 with Programmable Prescaler, Autoreload

and External Trigger

ADC 8-bit Analog-to-Digital Converter with 4 analog inputs

PWM

8 x 10-bit PWM/BRM

Fixed frequency for all outputs

6 x 8-bit PWM divided in 4 + 2 outputs with

programmable frequency per bank

InfraRed No Yes

Low Voltage Detector

(LVD)

Yes

In Circuit Debugging (ICD) No Yes (ICC)

In Circuit Programming

(ICP)

Yes (JTAG)

Program only (no erase)

Yes (ICC)

All sectors programmable/erasable

In Application

Programming (IAP)

No

Yes

4 Kbytes Upper Sector protected

Protection Against

Program Read-Out

No Yes

I/O Pins ST72T774 ST7FLCD1

Number of I/O Pins 31 22

Open Drain

4 x High Current Drive 10 mA

4 x Current Drive 3 mA

8 + 2 (ICC)

Current Drive 4mA

Push Pull 23

10

+ 2 High Current Drive 8 mA

STMicroelectronics Confidential 3/16

AN1581 Memory Map

2 Memory Map

The memory map of both devices follow a similar organization. Only RAM and Program Size may

differ:

In the ST7FLCD1 MCU, the larger RAM space available in Page 0 (192 bytes instead of 160) allows

better software optimization and speed, especially in C language.

Both Program Areas start at 1000h and end at FFFFh with the Interrupt & Reset Vectors Area.

Stack top is set at 01FFh on both MCUs and stack pointer goes downwards.

Memory map files are available in C and ASM languages for each MCU.

2.1 ICC and FLASH Programming Requirements

Certain areas of RAM and FLASH memory are used during ICC (ICD/ICP) and during

programming/erasure of the FLASH memory (ICP/IAP).

Refer to the ICC Manual, Flash Memory Manual and MCU Datasheet for further information.

Figure 1: Memory Map

0000h

RAM

Interrupt & Reset Vectors

Hardware Registers

0040h

16-bit Addressing

003Fh

0FFFh

0100h

01FFh

FFDFh

FFE0h

FFFFh

60KbytesFLASH

1000h

0200h

083Fh

0840h

52 Kbytes

4 Kbytes

SECTOR 0

4 Kbytes

SECTOR 1

SECTOR 2

Short Addressing

RAM (zero page)

Stack

2KbytesRAM

0000h

RAM

Interrupt & Reset Vectors

Hardware Registers

0060h

16-bit Addressing

005Fh

0FFFh

0100h

01FFh

FFDFh

FFE0h

FFFFh

60 Kbytes OTP

1000h

0200h

03FFh

0400h

Short Addressing

RAM (zero page)

Stack

1KbyteRAM

EDIDA

EDIDB

0600h

ST7FLCD1ST72T774

I/O Pin Descriptions AN1581

4/16 STMicroelectronics Confidential

3 I/O Pin Descriptions

Up to 22 I/O pins are available on the ST7FLCD1 MCU.

Depending on the usage of the internal cells (DDC, I2C, PWM, ADC, InfraRed, Timers, Interrupts or

ICC), the number of free I/O pins will decrease accordingly.

3.1 ICC Interface

The 2 ICC signals, ICCDATA and ICCCLK, are mapped onto PC[1:0].

They are standard open drain I/O pins, but during ICC communication (ICD and ICP), all write

accesses to the PCDR and PCDDR registers are blocked at core level (however, read accesses

work correctly).

Therefore, their use is restrained to comply with ICC requirements:

q They should be connected to pull-ups (e.g. 4.7 k = 1 mA maximum) on the application side.

q If used as inputs by the application, isolation (such as a serial resistor) must be implemented to

avoid any signal conflict with remote ICC tools, otherwise the ICC communication will not work.

q If used as outputs by the application, no important circuitry should be driven by those 2 pins,

otherwise the application may be damaged during ICC communication.

q During ICD (In Circuit Debugging), those 2 pins are not driven by the application (due to the

blocked write accesses) and would return ICC levels if read by the application software.

The suggested use for those 2 pins would be LED driving, or any other non critical driving.

Not being able to see the LEDs toggle during ICD, or seeing the LEDs toggle along with ICC

communication during ICD/ICP, will then be of lesser importance.

Refer to the ICC Manual and MCU Datasheet for further information.

ST7FLCD1 Cell Equivalent on ST72T774 Corresponding ST7FLCD1 I/O

ADC PB[7:4] PB[3:0]

I2C PB[3:2] PD[1:0]

DDC PB[1:0]

PD[3:2] DDCA

PD[5:4] DDCB

Timer B PA6 EXTRIG

InfraRed PB3 IFR

PWM PB[7:6] and PC[7:2] PA[5:0]

Buzzer PA5

External Interrupts PD[4:3] PA[7:6]

ICC PC[1:0]

Open Drain PA[6:3] and PB[3:0] PC[1:0] and PD[7:0]

STMicroelectronics Confidential 5/16

AN1581 I/O Pin Descriptions

3.2 High-Power Push-Pull Outputs

PA4 and PA5 may be configured as high output I/Os (sink and drain 8 mA instead of 2 mA) by

means of bits 2 and 1 of the MISCR register. This allows high current devices such as LEDs to be

driven directly.

MISCR REGISTER (MISCR)

Read/Write

Reset value:00h

7 6 5 4 3 2 1 0

0 0 0 0 0 PA5OVD PA4OVD 0

Watchdog with Lock-Up Protection AN1581

6/16 STMicroelectronics Confidential

4 Watchdog with Lock-Up Protection

The ST7FLCD1 watchdog cell has a slightly different prescaler value (50000) than the one inside

the ST727x4 family (49152) but the final delay until the watchdog reset occurs is roughly the same.

However, there is a new feature called Lock-Up Protection which prevents the software from

rewriting the WDGCR Control Register at too close intervals.

When a write to the WDGCR register occurs, an 8-bit counter starts. It disables any further write

access to the WDGCR register until 256 CPU clock cycles have elapsed: any write during this time

will be ignored, the WDGCR register will not be refreshed and the 8-bit counter restarts for another

256 CPU clock cycles delay.

This is a protection against a software which is locked up in a never-ending loop and permanently

rewrites the WDGCR register. Since the main watchdog counter will keep counting down, it will

ultimately lead to a reset that will safely restart the whole application.

Figure 2: Watchdog Lock-Up Protection Counter Example

ST7FLCD1ST72T774

WDGCR = FFh

WDGCR = FFh

WDGCR = FFh

Software Hang-up

Watchdog Counter

FFh

FFh

FF..FE..FD....C0..BFh

RESET

D0h

CFh

Watchdog Counter

FFh

FFh

NEVER

D0h

CFh

RESET

FFh

Software Flow

!

STMicroelectronics Confidential 7/16

AN1581 I2C Single Master Cell

5 I2C Single Master Cell

The cell is nearly identical for both MCUs.

5.1 Unique I2CSR Status Register and Acknowledge Failure Bit

The Acknowledge Failure bit has been moved from bit 4 of the former I2CSR2 register to bit 6 of the

unique I2CSR register, and the I2CSR2 register has been removed. This makes the I2C software

more compact since only a single status register is to be read/polled.

I2C STATUS REGISTER (I2CSR)

Read Only

Reset Value: 0000 0000 (00h)

5.2 Speed Control and Ultra High Speed

The I2CCCR Clock Control Register has a new bit 6 named FILTOFF instead of former speed

control bit 6 CC6. If set, this bit turns off certain noise filters inside the I/O pins to achieve speeds

higher than 400 kHz (up to 800 kHz depending on the CPU clock frequency).

But achieving such a speed is a violation of the I2C Fast Specification standard, therefore it is to be

done at the user's risk and on a short bus length only.

I2C CLOCK CONTROL REGISTER (I2CCCR)

Read / Write

Reset Value: 0000 0000 (00h)

The usual clock computation formula remains valid, but on 6 bits CC[5:0] instead of 7.

7 6 5 4 3 2 1 0

EVF AF TRA 0 BTF 0 M/IDL SB

7 6 5 4 3 2 1 0

FM/SM FILTOFF CC5 CC4 CC3 CC2 CC1 CC0

Display Data Channel (DDC) AN1581

8/16 STMicroelectronics Confidential

6 Display Data Channel (DDC)

The ST7FLCD1 MCU has 2 built-in Display Data Channel (DDC) cells named DDCA and DDCB.

They are completely independent, have their own DDC pins and their own dedicated DMA area in

RAM for DDC2B transfers.

The 2 DDC interfaces can run concurrently and both DMA can work at the same time (but in case of

simultaneous DMA requests, DDCA has priority over DDCB).

Each interface has its own identical set of registers of the same name except trailing letter "A" for

DDCA and "B" for DDCB.

6.1 DDC2B Handling

This DDC2B protocol is automatically handled and no software support is needed apart from the

proper initialization of the DDCDCR control register.

DDC2B CONTROL REGISTER (DDCDCR)

Read / Write

Reset Value: 0000 0000 (00h)

Only DDC2B addresses A0h/A1h are decoded. Former DDC1, P&D and FPDI-2 are no longer

handled. As such, there is no longer a VSYNC input (for DDC1) and former configuration bits CF2

CF1 and CF0 (former bits 6, 3 and 2) have been removed.

A new feature, called End Of Communication, detects NAK and STOP bits during a DDC2B read

transfer. This is to be used in conjunction with E-DDC protocol. The corresponding End Of

Communication Flag (ENDCF) and Interrupt Enable (ENDCE) are mapped onto bits 5 and 4.

End of Download Flag (EDF) and Interrupt Enable (EDE) are now mapped onto bits 3 and 2 instead

of former bits 5 and 4.

Bit 0 is now called "DDC2BPE" instead of "HWPE".

6.2 DDC Address Decoding

This cell is entirely driven by software. It may now decode up to 3 different sets of addresses instead

of just 2.

DDC CONTROL REGISTER (DDCCR)

Read / Write

Reset Value: 0000 0000 (00h)

7 6 5 4 3 2 1 0

0 0 ENDCF ENDCE EDF EDE WP DDC2BPE

7 6 5 4 3 2 1 0

0 0 PE DDCCIEN 0 ACK STOP ITE

STMicroelectronics Confidential 9/16

AN1581 Display Data Channel (DDC)

The DDC/CI address decoding (6Eh/6Fh) is now decoded by hardware instead of former E-DDC

addresses (60h/61h) of lesser use. The corresponding enable bit 4 is now called "DDCCIEN"

instead of "EDDCEN" and DDCSR2 bit 0 is now called "DDCCIF" instead of "EDDCF".

DDC STATUS REGISTER 2 (DDCSR2)

Read Only

Reset Value: 0000 0000 (00h)

The other bits of the DDCSR1 and DDCSR2 status registers remain unchanged.

The cell has now 2 programmable Own Address Registers 1 and 2 (DDCOAR1, DDCOAR2) instead

of 1. Therefore a maximum of 3 different addresses (DDC/CI + OAR1 + OAR2) may be decoded.

It allows greater flexibility and several DDC standards like E-DDC, HDCP, factory alignment etc..

can now be handled simultaneously.

When any of the 3 addresses is decoded on the DDC bus, the ADSL bit 2 in the DDCSR1 register

is set as usual.

Each DDCA and DDCB cell has its own set of OAR1 and OAR2 addresses which may be

independently set, e.g. for different address decoding over VGA-DDC and DVI-DDC buses.

7 6 5 4 3 2 1 0

0 0 0 AF STOPF 0 BERR DDCCIF

External Interrupts AN1581

10/16 STMicroelectronics Confidential

7 External Interrupts

The ST7FLCD1 has 2 external interrupts ITA and ITB with separate polarity control and interrupt

vectors. They can also be enabled or disabled independently by means of the ITRFRE register.

EXTERNAL INTERRUPT REGISTER (ITRFRE)

Read/Write

Reset value:00h

The former MISCR register still exists, but is dedicated to other uses (refer to Section 3: I/O Pin

Descriptions).

7 6 5 4 3 2 1 0

0 0 ITBEDGE ITBLAT ITBITE ITAEDGE ITALAT ITAITE

STMicroelectronics Confidential 11/16

AN1581 Timers

8 Timers

The former 16-bit Timer has been replaced by 2 distinct Timers named Timer A and Timer B.

They work almost the same way (a downcounter that starts from a preloaded value) but Timer A has

a buzzer output feature while Timer B can be triggered by an external signal.

Each timer has its own identical set of registers of the same name except trailing letter "A" for Timer

A and "B" for Timer B.

8.1 Timer A

TIMER CONTROL STATUS REGISTER A (TIMCSRA)

Read/Write

Reset Value: 0000 0000 (00h)

The timebase unit is configured by means of bits TB1 and TB0 which set the timebase prescaler.

When the downcounter reaches 00, an OverFlow (OVF) bit is set, and an interrupt is generated if

the OverFlow Enable (OVFE) bit is set. The OVF bit is cleared by reading the TIMCSRA register.

An autoreload of the downcounter with the contents of the TIMCPRA Preload Register may occur

when it reaches 00, if the Timer AutoReload (TAR) bit is set.

The buzzer output is mapped onto PA5 and is enabled if the BUZzer Enable (BUZE) bit is set. Its

frequency is configured by means of bits BUZ1 and BUZ0.

8.2 Timer B

TIMER CONTROL STATUS REGISTER A (TIMCSRA)

Read/Write

Reset Value: 0000 0000 (00h)

Timebase prescaler, overflow and autoreload are managed the same way as Timer A, except that

the timebase clock is faster than TIMER A (to achieve different delays).

The countdown can be started externally by means of the EXTRIG signal on PA6 if EXT=1. The

EDG bit selects the edge on EXTRIG that starts the countdown. Once detected, this edge sets the

EEF flag.

7 6 5 4 3 2 1 0

TB1 TB0 OVF OVFE TAR BUZ1 BUZ0 BUZE

7 6 5 4 3 2 1 0

TB1 TB0 OVF OVFE TAR EXT EDG EEF

Pulse Width Modulation (PWM) AN1581

12/16 STMicroelectronics Confidential

9 Pulse Width Modulation (PWM)

The 6 PWM push-pull outputs of the ST7FLCD1 are grouped in 2 banks of 4 and 2 outputs,

respectively.

Each bank has its own identical set of registers of the same name except trailing letter "A" for Bank

A (4 outputs PWM[3:0] mapped onto PA[3:0]) and "B" for Bank B (2 outputs PWM[5:4] mapped onto

PA[5:4]).

Each bank can also work at its own frequency by means of its respective AutoReload Register

(PWMARRA or PWMARRB).

Each PWM output can be enabled or disabled independently (bit OEx) and polarity controlled

independently (bit OPx) by means of the Control Register (PWMCR) of the relevant bank. The

polarity bit is no longer mixed with the PWM register.

CONTROL REGISTER A (PWMCRA)

Read/Write

Reset Value: 0000 0000 (00h)

CONTROL REGISTER B (PWMCRB)

Read/Write

Reset Value: 0000 0000 (00h)

The duty cycle of each PWM output can be set by means of the six PWMDCR[5:0] registers.

Each output has a resolution of 8 bits (one PWMDCR register per output). BRM bits no longer exist.

7 6 5 4 3 2 1 0

OE3 OE2 OE1 OE0 OP3 OP2 OP1 OP0

7 6 5 4 3 2 1 0

0 0 OE5 OE4 0 0 OP5 OP4

STMicroelectronics Confidential 13/16

AN1581 Infrared Controller (IFR)

10 Infrared Controller (IFR)

This cell is identical to the infrared cell of the ST7275-ST7277 Monitor MCU family.

It has a dedicated IFR input mapped onto PB3.

The cell is able to measure the delay (from 80 5s to 20.4 ms at fCPU = 8 MHz) between consecutive

IFR signal edges.

The edges to detect can be programmed as negative and/or positive by means of the NEGED and

POSED bits in the IFRCR Control Register:

INFRARED CONTROL REGISTER (IFRCR)

Read/Write

Reset Value: 0000 0000 (00h)

An additional glitch filter can filter out signals whose positive level is shorter than 2 5s or 160 5s, by

means of the FLSEL bit.

An interrupt may also be generated upon signal detection if the InTerrupt Enable (ITE) bit is set. The

internal interrupt flag must then be cleared by software by writing to the IFRDR Data Register.

If the interrupt is enabled but a signal is not detected, the built-in counter will generate an overflow

interrupt every 20.4 ms (at fCPU = 8 MHz). It can be used as a simple timebase.

Here is an example of the InfraRed detector wired to pin PB3:

7 6 5 4 3 2 1 0

0 0 0 ITE FLSEL POSED NEGED -

Figure 3: Example of External Infrared Circuitry

Infrared Detector

TSOP12, TFM1380 etc..

VDD

OUT

GND

3

2

1

to MCU pin IFR

to +5V

15K

4.7uF

In-Circuit Communication (ICC) Interface AN1581

14/16 STMicroelectronics Confidential

11 In-Circuit Communication (ICC) Interface

Through the ICC connector (HE-10 male connector), external devices can be connected to the

ST7FLCD1 MCU to do all the following actions with the MCU soldered on the application:

q In-Circuit Debugging (ICD): debug the application; some restrictions apply (only 2 breakpoints,

no trace, 2 I/Os dedicated to ICC..) but works otherwise in a similar fashion and under the

same STVD7 environment

q In-Circuit Programming (ICP): program the entire FLASH Memory; all sectors can be erased,

read and written without any restriction

Refer to the ICC Manual, Flash Memory Manual and MCU Datasheet for further information.

11.1 Memory Requirements for In-Circuit Debugging (ICD)

If the application is to be debugged using ICD, a specific area of the FLASH is used by the debugger

to upload routines of its own. This area is from FF00h to FFDFh and CANNOT be used by the

application software itself.

It is therefore strongly suggested to make provisions for future debugging needs, and consider this

small area "reserved" at the programming stage.

If ICD is never to be used, this area needs not be reserved and is free to be used for another

use.

Figure 4: ICD Memory Space

FFDFh

FF00h

FFFFh

SECTOR 0

Interrupt & Reset Vectors

FFE0h

Reserved for ICD

4 KBytes

FEFFh

F000h

Free Flash Memory

STMicroelectronics Confidential 15/16

AN1581 In-Application Programming (IAP)

12 In-Application Programming (IAP)

Programming and erasing the Flash Memory contents with the MCU soldered on the application

and running the application software is also possible. This is called In-Application Programming

(IAP).

To do this, part of the application software must contain routines that will handle programming and

erasure of Sector 1 (4 KBytes wide) and/or Sector 2 (52 KBytes wide) thru access to some specific

registers dedicated to Flash Memory management.

Refer to the Flash Memory Manual and MCU Datasheet for further information.

Such routines could use data fed to the MCU by means of external I/O pins, such as DDC for

example.

Application Notes specifically covering IAP are also available.

12.1 IMPORTANT NOTE: Protected Sector 0

The IAP routines must be located in the upper Sector 0 (4-KByte wide) of the Flash Memory since

this particular sector is protected against programming and erasure while in IAP Mode.

What can be taken as a restriction is actually a protection against software misbehavior during IAP.

Even if Sectors 1 and 2 are corrupted, Sector 0 (which contains the routines themselves and all

interrupt and reset vectors) always remains untouched and the MCU could restart correctly after a

reset. Then IAP could be run again to restore full MCU workability.

If Sector 0 was also corrupted, the MCU could not be reset and the whole application would be

stalled. In that case, the only possible choice would be to reprogram the entire Flash Memory

contents by means of ICP (which means connecting the ST7FLCD1 ICC pins to an HE-10

connector etc..).

12.2 IMPORTANT NOTE: Interrupts & Reset Vectors

Sector 0 cannot be programmed nor erased by means of IAP; this includes the interrupts and reset

vectors area. It is therefore strongly suggested to redirect all the above vectors to fixed vectors

locations either in Sector 1 or in Sector 2: should the interrupts or reset location change, the

vectors can be updated accordingly.

Figure 5: Memory Map and Sector Address

4 Kbytes

4 Kbytes SECTOR 1

SECTOR 0

SECTOR 2

60 Kbytes FLASH

FFFFh

EFFFh

DFFFh

1000h

MEMORY SIZE

52 Kbytes

In-Application Programming (IAP) AN1581

16/16 STMicroelectronics Confidential

"The present note which is for guidance only aims at providing customers with information regarding

their products in order for them to save time. As a result, STMicroelectronics shall not be held liable

for any direct, indirect or consequential damages with respect to any claims arising from the content

of such a note and/or the use made by customers of the information contained herein in connection

with their products."

Notes:

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its

use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously

supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without

express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

) 2002 STMicroelectronics - All Rights Reserved

STMicroelectronics GROUP OF COMPANIES

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