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Monitoring video synchronization signals on ST7FLCD1 MCU

Posted: 30 Nov 2004     Print Version  Bookmark and Share

Keywords:embedded 

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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

5th February 2003 Revision 1.0 1/7

By DTV - Monitor MCU Applications Lab

AN1659

Application Note

Monitoring Video Synchronization Signals

on ST7FLCD1 MCU

.

Introduction

On a monitor application, when the monitor has been put in power saving mode for energy saving

purposes, the activity in the monitor is kept to a minimum to achieve the lowest possible power

consumption.

However, the MCU must still be running and checking for any video signal that would `wake up' the

monitor from its standby state and back in to normal working operation.

For that purpose, monitoring of the incoming synchronization signals is mandatory: the MCU is

permanently monitoring its so-called sync inputs (horizontal, vertical and/or composite) and, in case

a new stable video mode is detected, it restarts the whole monitor.

This application note provides all the technical details on both the hardware and software sides of

how to implement such a sync monitoring technique.

It is particularly applicable to the ST7FLCD1 MCU, which provides two external interrupt inputs as

well as a fine delay timer, thus suited to performing all of the necessary monitoring operations.

1 Signals to Monitor

Most monitor applications take several possible video synchronization signals as inputs:

Horizontal sync signal, named HSYNC

Vertical sync signal, named VSYNC

Composite sync signal, named HVSYNC (if on the same HSYNC line) or CSYNC

Sync-on-Green signal (composite sync mixed with green colour signal), named SOG

Such signals come from the external video source, usually the PC that is connected to the display

by means of the VGA or DVI plug. For example, the signals mapped onto the VGA plug are:

Sync Signal VGA pin number

HSYNC or CSYNC 13

VSYNC 14

SOG

(mixed with Green)

2

Signals to Monitor AN1659

2/7

The composite sync signal CSYNC may be extracted from the SOG signal by means of a sync

extractor block, either internal or external to the MCU, as in the following example:

Note: Not all monitors provide SOG capability.

Each of the incoming sync signals must be routed to a dedicated pin on the MCU, so that the MCU

can monitor them independently and all at the same time.

The CSYNC signal may be combined with the HSYNC signal by means of an XOR gate, for

example:

That way, only 2 sync signals have to be monitored. This means one less pin (no separate pin for

SOG detection) and makes monitoring software simpler.

Note: An XOR gate is best used, rather than an OR gate, because if either signal is stuck high, the XOR

gate output will still toggle with the 2nd

input, while the output of an OR gate would remain high.

Inputplug

HSYNC/HVSYNC

VSYNC

CSYNCGreen

VGA cable

Sync

Extractor

Monitor

Board

MCU

Inputplug

HSYNC/HVSYNC

VSYNC

CSYNC

Green

Monitor

Board

Sync

Extractor

ITA

ITB

MCU

3/7

AN1659 Signals Monitoring

2 Signals Monitoring

When a picture is issued by the PC (or any other external source), some of the signals mentioned

above toggle at fixed frequencies.

When the MCU detects activity on a signal, it monitors the signal for some time to distinguish

between a known stable signal and a glitch. This avoids having the monitor exit from standby state

whenever a glitch is mistaken for a real video signal.

2.1 External Interrupts Flags

The sync signals are routed to the 2 external interrupt pins ITA and ITB built in the ST7FLCD1

MCU.

Each pin has separate polarity control, detection flag and interrupt capabilities. In this case, the

detection flag will be used alone. There is no real need to trigger an interrupt on an incoming signal,

unless the main software loop takes too much time and is unable to monitor the incoming signals

regularly enough.

These control bits belong to the ITRFRE register:

EXTERNAL INTERRUPT REGISTER (ITRFRE)

Read/Write

Reset value: 00h

Whenever the desired edge (ITAEDGE and ITBEDGE bits) is sensed on either ITA or ITB, its

respective flag ITALAT or ITBLAT is set. Once set, this flag can only be reset by software. This

perfectly fits our needs to monitor the signals:

Reset the ITxLAT flag

Read the ITxLAT flag on a regular basis:

if the flag is still reset: no signal was detected, continue

if the flag is found set: a signal was detected, proceed with glitch filtering

2.2 Glitch Filtering

Once a signal has been detected, the software must filter out all the glitches that can occur over the

sync signal lines.

To do this, a software delay is implemented by means of a timer. This algorithm is run after either

flag (ITALAT or ITBLAT) was found set:

Clear the ITxLAT flag

Start a delay depending on the signal (HSYNC or VSYNC)

Wait until the end of the delay

Read the ITxLAT flag again:

if the flag is still reset: the signal was actually a glitch, ignore and continue

if the flag is found set: the signal may be a stable sync signal, proceed with analysis

7 6 5 4 3 2 1 0

0 0 ITBEDGE ITBLAT ITBITE ITAEDGE ITALAT ITAITE

Signals Monitoring AN1659

4/7

The TIMER B is used to generate such a delay. It is programmed in one-shot mode (no autoreload,

no external trigger) in the TIMCSRB control register:

TIMER CONTROL STATUS REGISTER B (TIMCSRB)

Read/Write

Reset Value: 00h

The delay is programmed by means of its associated TIMCPRB register, for a given duration

depending on the sync signal to monitor:

Monitoring HSYNC: set delay to min. acceptable Hfreq (e.g. 1005s for Hfreqmin=10kHz)

Monitoring VSYNC: set delay to min. acceptable Vfreq (e.g. 20ms for Vfreqmin=50Hz)

When the programmed delay has elapsed, the overflow flag OVF is set. It must be reset by reading

TIMCSRB.

If the ITxLAT flag is found set again, this means that another pulse has been detected during the

given delay, therefore it may be a stable sync signal.

Note: In case of HSYNC, the delay value is 100us, therefore the other TIMER A is not suited for this

application (its minimum timebase value being 2285s at fCPU = 9MHz) unless the chosen minimum

sync period exceeds that value.

7 6 5 4 3 2 1 0

TB1 TB0 OVF OVFE TAR EXT EDG EEF

5/7

AN1659 Complete Software Algorithm

3 Complete Software Algorithm

Reset ITALAT and ITBLAT flags

Stop TIMER B

Main loop

(takes some time)

ITALAT == 1 ?

ITBLAT == 1 ?

Write TIMCPRB

(1005s duration)

OVF == 1 ?

ITALAT == 1 ?

Clear ITALAT

HSYNC

detected

Y

N

N

Y

Was a glitch

Write TIMCPRB

(20ms duration)

OVF == 1 ?

ITBLAT == 1 ?

Clear ITBLAT

VSYNC

detected

Y

N

N

Y

Was a glitch

Y

Y

N

N

Continue

Edge on HSYNC

Edge on VSYNC

SyncDetect_Init()

SyncDetect()

Software Example AN1659

6/7

4 Software Example

The following software example is written in C language, easily portable to assembly language if

required. The TIMER B time frames are fitted for a 27MHz external clock (fCPU=9MHz).

Two routines are created:

SyncDetect_Init() which resets the ITxLAT flags and stops the TIMER B

SyncDetect() which handles the main HSYNC and VSYNC detection routines

Both appear as dotted blocks on the algorithm in Chapter 3.

void SyncDetect_Init (void) {

TIMCSRB= 0x00; // disable TIMER B auto-reload

ITRFRE = 0x00; // ITA and ITB on falling edge, no interrupt,

// clear external detection flags

}

void SyncDetect (void) {

unsigned char qHActive = 0, qVActive = 0;

if ( !(ITRFRE & 0x12) )// return if ITBLAT=0 and ITALAT=0

return; // continue if either bit is set

// Process HSYNC first

if ( ITRFRE & 0x02 ) { // if ITA ==> HSYNC

ITRFRE &= ~0x02; // clear ITALAT bit

TIMCSRB = 0x00; // timebase period = 14.2us at fCPU=9MHz

TIMCPRB = 7; // delay = 7 x 14.2us = 100us --> Hmin=10kHz

while (!(TIMCSRB & 0x20));

// loop until (OVF = 1) the programmed delay has elapsed

if ( ITRFRE & 0x02 ) { // if another Hpulse

qHActive = 1;

}

}

// Process VSYNC Similarly

if ( ITRFRE & 0x10 ) { // if ITB ==> VSYNC

ITRFRE &= ~0x10; // clear ITBLAT bit

TIMCSRB = 0x80; // timebase period = 228us at fCPU=9MHz

TIMCPRB = 88; // delay = 88 x 228us = 20ms --> Vmin=50Hz

while (!(TIMCSRB & 0x20));

// loop until (OVF = 1) the programmed delay has elapsed

if ( ITRFRE & 0x10 ) { // if another Vpulse

qVActive = 1;

}

}

if ( qHActive || qVActive) {

// *************************************

// further processing occurs here

// *************************************

}

7/7

AN1659 Software Example

If a signal was detected repeatedly on HSYNC and within 1005s time frame, the flag qHActive is

set.

If a signal was detected repeatedly on VSYNC and within 20ms time frame, the flag qVActive is set.

Further processing, depending on the detected signals (HSYNC and/or VSYNC) must be done

within the SyncDetect() routine. Otherwise the routine must be modified to return a status byte, and

then the processing can be done outside the routine.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its

use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously

supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without

express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

) 2003 STMicroelectronics - All Rights Reserved

STMicroelectronics GROUP OF COMPANIES

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www.st.com





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