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ISP1581/2/3 frequently asked questions

Posted: 09 Jun 2005     Print Version  Bookmark and Share

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AN10046

ISP1581/2/3 Frequently Asked Questions

Rev. 02 -- 27 April 2005 Application note

Document information

Info Content

Keywords isp1581, isp1582, isp1583, faq, usb, universal serial bus

Abstract This document is a compilation of Frequently Asked Questions (FAQs) on

Philips high-speed and full-speed Universal Serial Bus Peripheral

Controllers: the ISP1581, ISP1582 and ISP1583.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 2 of 18

Contact information

For additional information, please visit: http://www.semiconductors.philips.com

For sales office addresses, please send an email to: sales.addresses@www.semiconductors.philips.com

Revision history

Rev Date Description

02 20050427 Second release. Added Question 2.12, Question 2.13 and Question 2.14. Updated Fig 10.

01 20050301 First release.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 3 of 18

1. General product information

1.1 What are the differences between the ISP1581, ISP1582 and

ISP1583?

The ISP1581/2/3 are cost-optimized and feature-optimized Hi-Speed Universal Serial

Bus (USB) Peripheral Controllers. They fully comply with Universal Serial Bus

Specification Rev. 2.0; supporting data transfer at high-speed (480 Mbit/s) and full-speed

(12 Mbit/s).

Table 1: lists the major differences between the ISP1581, ISP1582 and ISP1583.

Table 1: Characteristic differences between the ISP1581, ISP1582 and ISP1583

Characteristic ISP1581 ISP1582 ISP1583

Bus configuration Generic and split bus Generic Generic and split bus

ATA/ATAPI interface Yes No Yes

Power supply 5 V or 3.3 V (internal

regulator)

3.3 V (no internal

regulator)

3.3 V (no internal

regulator)

I/O voltage 5 V or 3.3 V (internal

regulator)

3.3 V 1.65 V to 3.6 V

Operating current 130 mA (high-speed) 45 mA (high-speed)

17 mA (full-speed)

47 mA (high-speed)

19 mA (full-speed)

Suspend current 450 5A (typical) 160 5A (typical) 160 5A (typical)

PIO RD/WR cycle time 80 ns 50 ns 50 ns

DMA slave RD/WR

cycle time

78 ns 75 ns 75 ns

VBUS sensing support No Yes Yes

Package LQFP64 HVQFN56 HVQFN64

2. Interfacing

2.1 Why should the IN endpoint buffer be properly cleared in the

ISP1582/3?

If the USB connector is suddenly disconnected in the midst of a data transfer, there may

be residual data in the IN endpoint buffer. This may cause data corruption during the next

data transfer. To avoid data corruption, the IN endpoint buffer must be properly cleared.

For details on clearing the IN endpoint buffer, refer to ISP1582/83 Clearing an IN Buffer

(AN10045) application note.

2.2 What is the fastest transfer speed achievable on the ISP1582/3?

For back-to-back data access--for both read and write--maintain a minimum cycle time

of 50 ns (see Fig 1).

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 4 of 18

Fig 1. Back-to-back data access.

If the access is from write to read-or-write data on a different address, then the access

time should be at least 91 ns. This also applies for read-or-write data to write access.

Fig 2 shows the read-to-read access of the Scratch register and the Chip ID register.

Fig 2. Read-to-read access of various addresses.

Fig 3 shows the write-to-write access to the Address register and the Interrupt

Configuration register.

Fig 3. Write-to-write access of various addresses.

Fig 4 shows the write-to-read access of the Interrupt Configuration register and the Chip

ID register.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 5 of 18

Fig 4. Write-to-read access of various registers.

Fig 5 shows the read-to-write access on the Chip ID register and the Interrupt

Configuration register.

Fig 5. Read-to-write access of various registers.

2.3 When should the Buffer Length register and the Validate bit be used?

The Buffer Length register is used when the number of bytes is predetermined and buffer

length validation is not required. It is useful when operating in generic processor mode--

16-bit data and 8-bit address--for an odd number of bytes. When an OUT token with

zero-length packet is received, the Buffer Length register will reflect zero.

The Validate bit is used when the number of bytes to be sent to the IN endpoint is not

predetermined. It is only used for an even number of bytes, when operating in generic

processor mode. There is no restriction when in split bus mode.

Do not use the Buffer Length register together with the Validate bit because this will

result in error.

2.4 What should be done if a suspend interrupt occurs along with a

resume interrupt?

If a suspend interrupt occurs along with a resume interrupt, clear both the suspend the

and resume interrupts. Do not service them.

Table 2: lists the conditions to service suspend and resume interrupts.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 6 of 18

Table 2: Conditions to service the suspend and resume interrupts

Suspend Resume Action

0 1 Clear resume. Service resume.

1 0 Clear suspend. Service suspend.

1 1 Clear both suspend and resume. Do not service them.

2.5 Should control endpoints be also initialized when initializing other

endpoints?

No. Control endpoints are self-initialized and are fixed at 64 B. Do not initialize control

endpoints. Initializing control endpoints will result in errors.

2.6 Why is a transistor or MOSFET circuit needed on the VBUS pin of the

ISP1581?

The circuit is needed for the USB Compliance check. For a self-powered system, the

Back-Voltage Test in the USB Compliance checks the voltage of VBUS, DP and DM with

respect to the ground, when the device is unplugged from a host or the host is

suspended. The requirement for the Back-Voltage Test is that the voltage must not

exceed 400 mV, after the device is unplugged or the host is suspended.

It is recommended that you have an external transistor or MOSFET to prevent back

voltage on the DP and DM lines when the host is suspended or when the USB cable is

disconnected. This is because the ISP1581 does not have any built-in VBUS sensing. With

the transistor or MOSFET acting as a VBUS sensing, you can leave SoftConnect

permanently on, and the transistor will handle the supply of 3.3 V to RPU with respect to

the VBUS presence.

Fig 6 shows the transistor or MOSFET circuit as well as the block diagram of the

SoftConnect portion of the ISP1581.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 7 of 18

Fig 6. Transistor or MOSFET circuit.

2.7 Is it possible for the microcontroller to enable SoftConnect, when

VBUS is not present?

This is not advisable because it will cause a failure of the Back Voltage Compliance Test.

SoftConnect should be enabled on detecting the presence of VBUS.

For details, see Table 3:.

Table 3: Status of the chip

VBUS SoftConnect Comments

Present On

Pull-up resistor on DP

Back voltage is not measured because

enumeration process will begin

Not present Off

Pull-up resistor on DP is removed;

suspend interrupt after 3 ms of no bus

activity

Back voltage will be measured

2.8 In the Mode register of the ISP1582/3, how does the wake-up on chip

select (WKUPCS) work?

The ISP1582/3 can be woken up using the wake-up on chip-select function. To use this

function, the WKUPCS bit must be set to logic 1 before the ISP1582/3 enters suspend

mode. To wake-up the ISP1582/3, assert the chip select and perform a valid register

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 8 of 18

read. The reading of registers must be done within the ISP1582/3 address range. CS_N

and RD_N must be asserted together for the ISP1582/3 to wake up from suspend mode.

Performing a valid register write is not recommended because registers may be locked

from writing after the ISP1582/3 goes into suspend mode.

2.9 In the ISP1582/3, how long does it take for VBUS to charge and

discharge?

It takes VBUS about 22 ms to charge and 1.8 sec to discharge. This measurement is done

using a 10 k series resistor, in addition to 1 M and 1 5F on VBUS.

It is recommended that you connect a10 k to 200 k series resistor on VBUS as an

additional protection for the VBUS pad.

Fig 7 shows the connection diagram for VBUS.

Fig 7. VBUS connection diagram.

Fig 8 shows the waveform for the charging of VBUS.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 9 of 18

Fig 8. VBUS charging waveform.

Fig 9 shows the waveform for the discharging of VBUS.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 10 of 18

Fig 9. VBUS discharging waveform.

2.10 How to configure the ISP1583 in GDMA master mode?

Perform the following settings to configure the ISP1583 DMA as a master in non-ATA

mode:

7 DMA Configuration register (38h): the ATA_MODE bit is set to logic 1 configures

the DMA for MDMA mode.

7 DMA Hardware register (3Ch), the MASTER bit is set to logic 1 the ISP1583 is

configured in Generic DMA (GDMA) master mode.

When you are using the ISP1583 as DMA master, DREQ will act as an input pin, and

DACK, DIOR and DIOW will act as output pins. The DREQ signal must be asserted

(active HIGH by default) for any DMA activities. If no activity is seen after asserting

DREQ, ensure that the EOT pin is not asserted.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 11 of 18

2.11 In the ISP1583, how to interface to the ColdFire processor using the

Generic Processor mode in the ISP1582 and Split Bus mode?

Fig 10. Example for interfacing the ISP1583 MP3 application in split bus mode.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 12 of 18

Fig 11. Example for interfacing the ISP1582 MP3 application in generic processor mode.

Remark: Question 2.12, Question 2.13 and Question 2.14 are related to Philips

application note Interfacing the ISP1582 to the Intel PXA250 Processor (AN10038). For

details, refer to the application note.

2.12 Why must an OR operation be performed between ADDR24 and

ADDR25 for CS_N?

An OR operation must be performed between ADDR24 and ADDR25 in generic

processor mode to determine whether it is a PIO or DMA range, that is, a PIO transfer or

a DMA transfer.

PIO transfer: CS_N will be asserted for PIO transfer; see Fig 12.

Fig 12. PIO transfer in generic processor mode example.

DMA transfer: CS_N will be deasserted for DMA transfer; see Fig 13. For DMA mode,

CS_N is not needed and should be masked off.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 13 of 18

Fig 13. DMA transfer in generic processor mode example.

PIO or DMA transfer: If you are using the following address range, then you can just OR

ADDR25 and HCS2# because ADDR24 is always 0; see Fig 14. If, however, you are

using a different address range, then Fig 12 and Fig 13 must be implemented, that is, OR

ADDR24 and ADDR25.

7 PIO address range: 00000000h to 00FFFFFFh

7 DMA address range: 02000000h to 02FFFFFFh.

Fig 14. PIO or DMA transfer in generic processor mode example.

2.13 Why must an OR operation be performed between ADDR25 and

CS_N for DACK?

DMA transfer: ADDR25 is needed for the DACK pin because the DACK signal is needed

when performing DMA. XScale provides the DACK signal through a logic process.

7 PIO address range: 00000000h to 00FFFFFFh

7 DMA address range: 02000000h to 02FFFFFFh

Fig 15. DMA transfer in generic processor mode example.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 14 of 18

In Fig 15, if ADDR25 is set to 1, it will become 0 after going through the inverter. Both the

outputs--inverter and HCS2#--will go through the OR gate and output as 0. DACK in the

ISP1582/3 is active LOW by default and so DACK is set.

2.14 Why must A[9:2]of PXA250 be connected to A[7:0] of the ISP1582/3?

The ISP1582/3 is a 16-bit data bus. When you connect A[9:2] of PXA250 to A[7:0] of the

ISP1582/3, the word alignment is perfect because the processor is 32 bits and there is

no performance problem.

3. Clocking

3.1 What should be the voltage swing if an external clock is used on the

ISP1582 or ISP1583?

For the ISP1582/3, the voltage swing for the external clock should be 1.8 V. The

ISP1582/3 will not function if 3.3 V is supplied. Fig 16 shows the capacitor circuit that can

successfully lower the swing from 3.3 V down to 1.8 V.

Fig 16. Capacitor circuit to lower the swing from 3.3 V to 1.8 V.

Fig 17 shows the input swing of 3.3 V using a function generator.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 15 of 18

Fig 17. Input swing of 3.3 V, before adding the capacitance circuit.

Fig 18 shows that the 3.3 V swing is lowered to 1.8 V after the capacitance circuit is

added.

Fig 18. Input swing is reduced to 1.8 V, after adding capacitance circuit.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 16 of 18

3.2 How long does it take for the clock to stabilize if the ISP1582/3 wakes

up on chip select?

As tested, it takes about 600 ns for the clock to stabilize if the ISP1582/3 wakes up on

chip select. This timing, however, may not be sufficient for the chip. This is because the

internal oscillator will take more than 500 5s to start up while the Phase-Locked Loop

(PLL) takes another 500 5s to start up. It is, therefore, recommended that you wait for a

minimum of 2 ms before performing a write or read operation.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Application note Rev. 02 -- 27 April 2005 17 of 18

4. Disclaimers

Life support -- These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status `Production'),

relevant changes will be communicated via a Customer Product/Process

Change Notification (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products

are free from patent, copyright, or mask work right infringement, unless

otherwise specified.

Application information -- Applications that are described herein for any of

these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the specified use without further testing or modification.

5. Trademarks

Notice -- All referenced brands, product names, service names and

trademarks are the property of their respective owners.

SoftConnect -- is a trademark of Koninklijke Philips Electronics N.V.

Philips Semiconductors AN10046

ISP1581/2/3 FAQs

) Koninklijke Philips Electronics N.V. 2005

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner. The information presented in this document does

not form part of any quotation or contract, is believed to be accurate and reliable and may

be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under

patent- or other industrial or intellectual property rights.

Date of release: 27 April 2005

Published in The Netherlands

6. Contents

1. General product information..............................3

1.1 What are the differences between the ISP1581,

ISP1582 and ISP1583? ......................................................3

2. Interfacing............................................................3

2.1 Why should the IN endpoint buffer be properly

cleared in the ISP1582/3?...................................................3

2.2 What is the fastest transfer speed achievable on

the ISP1582/3? ...................................................................3

2.3 When should the Buffer Length register and the

Validate bit be used? ..........................................................5

2.4 What should be done if a suspend interrupt

occurs along with a resume interrupt? ................................5

2.5 Should control endpoints be also initialized when

initializing other endpoints?.................................................6

2.6 Why is a transistor or MOSFET circuit needed on

the VBUS pin of the ISP1581? ..............................................6

2.7 Is it possible for the microcontroller to enable

SoftConnect, when VBUS is not present?.............................7

2.8 In the Mode register of the ISP1582/3, how does

the wake-up on chip select (WKUPCS) work?....................7

2.9 In the ISP1582/3, how long does it take for VBUS

to charge and discharge? ...................................................8

2.10 How to configure the ISP1583 in GDMA master

mode? .........................................................................10

2.11 In the ISP1583, how to interface to the ColdFire

processor using the Generic Processor mode in the

ISP1582 and Split Bus mode? ..........................................11

2.12 Why must an OR operation be performed

between ADDR24 and ADDR25 for CS_N? .....................12

2.13 Why must an OR operation be performed

between ADDR25 and CS_N for DACK?..........................13

2.14 Why must A[9:2]of PXA250 be connected to

A[7:0] of the ISP1582/3?...................................................14

3. Clocking .............................................................14

3.1 What should be the voltage swing if an external

clock is used on the ISP1582 or ISP1583?.......................14

3.2 How long does it take for the clock to stabilize if

the ISP1582/3 wakes up on chip select? ..........................16

4. Disclaimers ........................................................17

5. Trademarks........................................................17

6. Contents.............................................................18





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