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Interference Control during mixed-signal (analog and digital) board design

Posted: 30 Nov 2004     Print Version  Bookmark and Share

Keywords:analog and digital 

Mixed-Signal (Analog and Digital) Board Design

In a mixed-signal circuit, using both analog and digital components, the fast speed digital circuit section is

always a potential source of noise, especially for the sensitive analog circuit section.

/

PDF document

1/13October 2004

AN2010

APPLICATION NOTE

Interference Control during

Mixed-Signal (Analog and Digital) Board Design

In a mixed-signal circuit, using both analog and digital components, the fast speed digital circuit section is

always a potential source of noise, especially for the sensitive analog circuit section. The typical CMOS

digital device has a very low quiescent current, but study shows that simultaneous switching noise (SSN,

also known as ground bounce), caused by CMOS circuit switching current, forms the major contribution

to the overall circuit noise.

This application note describes how to deal with these problems, using an Analog-to-Digital converter as

an example. The 90C7101 ADC Verification board is an internal verification tool, used by ST, and is not

publicly available. However, it is used here as an illustrative example, since the PCB design rules are ap-

plicable to any board design.

The 90C7101 Turbo-Lite microcontroller is a mixed-signal SOC chip that incorporates an Analog-to-Digital

Converter (ADC), an 8-bit microcontroller, and various peripherals. The on-chip converter consists of an

8-input analog multiplexer, and a 10-bit binary successive approximation ADC. To achieve the 10-bit res-

olution, special attention should be paid to minimize the interference between digital and analog circuits.

Figure 1. 90C7101 ADC Block Diagram

VREF

AI10209

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

AVREF

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

Analog

MUX

10-Bit SAR ADC

Control

Select

ADCOUT - 10 Bits

ACON Register ADAT0 Register

ADAT1

Register

2/13

AN2010 - APPLICATION NOTE

TABLE OF CONTENTS

Figure 1. 90C7101 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

INTERFERENCE ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Current Flow through the Reactive Parasitic Components of a CMOS Output . . . . . . . . . 3

Figure 3. Current Flow through a CMOS Invertor, while its Output is Switching . . . . . . . . . . . . . . . 4

Figure 4. Lumped Parasitic Model of 90C7101 Power Lane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

GENERAL DESIGN GUIDE FOR ADC CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

90C7101 ADC VERIFICATION BOARD DESIGN CONSIDERATION . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 5. ADC Verification Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Separate Power Supply Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Reduced Digital Switching Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Track Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

APPENDIX A.COMPONENT PLACEMENT AND SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 7. 90C7101 ADC Verification Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 8. 90C7101 ADC Verification Board MCU PSD Schematic. . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 9. 90C7101 ADC Verification Board Power Supply Schematic . . . . . . . . . . . . . . . . . . . . . . 11

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 1. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3/13

AN2010 - APPLICATION NOTE

INTERFERENCE ANALYSIS

Figure 2. illustrates the circuit model of a CMOS output pad. CMOS devices operate by charging and dis-

charging a capacitive load. When the output changes state from High to Low or Low to High, a current

flows in the output loop. This current determines the output edge rate.

Figure 2. Current Flow through the Reactive Parasitic Components of a CMOS Output

CL

AI10237

LInput LOutput

LPower

PCB Power

LGnd

I(t)

4/13

AN2010 - APPLICATION NOTE

Figure 3. shows a CMOS inverter. When a High (H) signal is applied at the input, the upper p-channel

transistor is off and the lower n-channel transistor is on. The output is pulled to ground (Low) through the

conducting n-channel. Similarly, when a Low (L) signal is applied at the input, the n-channel is off and the

p-channel is on, pulling the output high through the conducting p-channel. When changing states from

High to Low, the p-channel begins to turn off and the n-channel begins to turn on. In the threshold region

(VIL < Vinput < VIH), both these transistors are partially ON, causing a through current, ICC, to flow from

VCC to GND. A similar situation exists when the output switches from Low to High.

Figure 3. Current Flow through a CMOS Invertor, while its Output is Switching

When the switching current flows over the parasitic inductor on the power lane, a noise voltage is gener-

ated. The 90C7101 features an 8-bit microcontroller which can work, at a maximum of 40MHz, with a

memory bus cycle as short as 100ns. It is essential to isolate SSN caused by microcontroller section out

of the analog section. 90C7101 has been designed to minimize digital-analog crosstalk by providing sep-

arated power and ground pins for its analog and digital sections. The analog section has dedicated analog

supply (AVCC and AGND) as well as reference voltage input (VREF).

ICC

AI10210

OutIn

LPower

PCB Power

LGnd

5/13

AN2010 - APPLICATION NOTE

To make full use of 10-bit resolution of 90C7101's ADC, special attention should be paid to the PCB de-

sign. Figure 4. illustrates a common circuitry connection with parasitic impedance shown at each power

lane.

Figure 4. Lumped Parasitic Model of 90C7101 Power Lane

In Figure 4.:

P1 is the joint point of analog ground and digital ground, while P2 is the joint point of analog power

and digital power.

L1 and L3 represent parasitic inductor of the copper tracks that connect AGND to P1 and DGND to

P1 respectively.

L2 and L4 represent parasitic inductor of the copper tracks that connect AVCC to P2 and DVCC to P2

respectively.

L5 and L6 represent parasitic inductor of the copper track that connects P1 to power supply negative

end and P2 to power supply positive end respectively.

Rs represents the internal serial resistance of power supply.

AI102XX

+

-

Input

VREF

Analog

Section

Digital

Section

90C7101

A-D

L1 L2 L3 L4

CA CA

AVCCAGND DVCCDGND

L6L5 RS

+-

VS

CS

P1 P2

6/13

AN2010 - APPLICATION NOTE

Each of these parasitic impedances has a different impact on the distribution of the SSN, depending on

the route of the switching current. Taking the power supply's negative terminal as the reference point, the

switching current flows over L3-P1-L5-Rs-L6-P2-L4.

P1 and P2 are made noisy by a voltage drop on L5 and L6, respectively, which will further affect the analog

circuit.

Voltage drops at L3 and L1 make the analog and digital sections work at different ground levels, which will

further affect the signal interface between the analog and digital sections ("A-D" in Figure 4.).

L3 restrains the switching current of the digital section. However, the limited current source leads to a low

slew rate of the digital circuit, which may cause a timing error in curtain conditions.

L2, on the other hand, has the benefit of isolating the high-frequency switching noise out of the analog

section. As the analog section often consumes a small, low-frequency current, L2 does not affect the nor-

mal operation of the analog section in the same way that L3 does to the digital section.

GENERAL DESIGN GUIDE FOR ADC CIRCUIT

The common approach to isolating SSN interference is through rigorous decoupling and grounding. The

following discussion lists some basic rules that need to be observed.

Use a separate analog and digital ground plane.

Ensure that the connection between each supply pin, and the corresponding power/ground plane, is

as short as possible.

In a single supply system, use the negative terminal of the capacitor, Cs, as the star point of the analog

and digital ground plane, and the positive terminal of the capacitor as the star point of the analog and

digital power plane. In this way, any common ground impedance will be eliminated by its parallel

connection with Cs.

The 90C7101 AGND terminal should serve as a star point for all analog ground connections, such as

any reference voltages, and analog input signals. The 90C7101 DGND terminal should serve as a star

point for all digital ground connections.

Use two capacitors which differ in value by at least a factor of ten (typically 15F and 0.15F) to decouple

the IC power pins.

Use three capacitors (typically 1005F, 4.75F, 0.15F) to decouple the power supply.

Use SMD Tantalum capacitors for values greater than 4.75F, and COG or X7R capacitors for those

less than 2.25F. The use of Z5U capacitors in high-resolution mixed-signal circuit is not

recommended.

Keep all bypass capacitors as close to the power pins of the device as possible.

An inductor may be inserted into the L2 branch if necessary.

90C7101 ADC VERIFICATION BOARD DESIGN CONSIDERATION

To verify the resolution of the ADC at the board level, it is necessary to create an extremely clean envi-

ronment that isolates any possible digital interference from the analog circuit. The 90C7101 ADC verifica-

tion board adopts the following approaches to eliminating the digital-to-analog crosstalk.

7/13

AN2010 - APPLICATION NOTE

Figure 5. ADC Verification Board Block Diagram

Separate Power Supply Scheme

The verification board is designed to amount separated voltage regulators as shown in Figure 4.. VREG1

is dedicated to service the 90C7101, and VREG2 powers the other digital section, which includes the PSD,

the oscillator, and the UART level shifter. The oscillator and the UART level shifter are either high frequen-

cy or high power. A dedicated regulator is essential to isolate these highly-noisy components from the IC

under test.

The voltage reference adopts MAX6129_EUT30, which features a 3V output, 0.4% accuracy, and 4mA

output source current. The reference is directly sourced from the 5V power supply.

Reduced Digital Switching Current

The SSN source switching current greatly depends on the capacitive load on the 90C7101's output pad.

To reduce the capacitive load, the verification board has been designed to be a minimum system for the

90C7101 microprocessor, consisting mainly of the PSD and oscillator. The sampled ADC data may be

sent out, for monitoring, through the serial interface. All input-only pads are pulled up, and all unused bi-

directional pads are configured in output mode by the firmware.

Power Track Layout

The ground terminals, of the three regulators, are joined together at point-G, which is the voltage reference

point for the whole board. It is also the star point of the analog and digital power planes. The ground pins,

of the analog and digital circuit sections, are connected to point-G through a separate, low impedance,

power plane. This reduces the digital-to-analog crosstalk to minimum.

AI10219

L

Analog

Section

Digital

Section

Voltage

Reference

PSD

UART

CLOCK

Power PlugVreg0

(5V)

Vreg2

(3.3V)

Vreg1

(3.3V)

Input

Amplifier

90C7101

AGND AVCC AGNDAVCC DVCC DVCCDGND DGND

DGND1 DGND2AGND

G

8/13

AN2010 - APPLICATION NOTE

APPENDIX A. COMPONENT PLACEMENT AND SCHEMATICS

Figure 6. Board Layout

AI10220

9/13

AN2010 - APPLICATION NOTE

Figure 7. 90C7101 ADC Verification Board Layout

AI10221

123456

A

B

C

D

654321

D

C

B

A

Title

NumberRevisionSize

B

Date:8-Jun-2004Sheetof

File:D:\ww\Projects\Protel\VeriADC.ddbDrawnBy:

MCU

MCU.SCH

Power

Power.SCH

90C7101ADCVerificationBoard

31

ChinaMMCC

10/13

AN2010 - APPLICATION NOTE

Figure 8. 90C7101 ADC Verification Board MCU PSD Schematic

AI10222

123456

A

B

C

D

654321

D

C

B

A

Title

NumberRevisionSize

B

Date:8-Jun-2004Sheetof

File:D:\ww\Projects\Protel\VeriADC.ddbDrawnBy:

ALE

6

TDO

7

TDI

8

TDO???

9

DEBUG

10

DVCC

12

DGND(IO)

14

TCK

17

TMS

18

SPISSEL/PCA1/P4.7

19

SPITXD/TCM5/P4.6

20

TMS???

31

SPIRXD/TCM4/P4.5

32

SPISCLK/TCM3/P4.4

33

TXD2/PCA0/P4.3

34

DGND(Core)

35

RXD2/TCM2/P4.2

36

T2x/TCM1/P4.1

37

T2/TCM0/P4.0

38

RXD1/P3.0

39

TXD1/P3.1

40

AD0/P0.0

41

AD1/P0.1

42

INT0/P3.2

43

AD2/P0.2

44

INT1/P3.3

45

AD3/P0.3

46

C0/P3.4

51

AD4/P0.4

52

C1/P3.5

53

AD5/P0.5

54

I2CSDA/P3.6

55

AD6/P0.6

56

I2CSCL/P3.7

57

AD7/P0.7

58

XTAL1

59

XTAL2

60

AD8/P2.0

62

ADC0/T2/P1.0

63

AD9/P2.1

64

ADC1/T2x/P1.1

65

AD10/P2.2

66

ADC2/RXD2/P1.2

67

AD11/P2.3

68

ADC3/TXD2/P1.3

69

AD12/P2.4

70

ADC4/SPISCLK/P1.4

71

AD13/P2.5

72

ADC4/SPIRXD/P1.5

73

AD14/P2.6

74

ADC6/SPITXD/P1.6

81

AD15/P2.7

75

ADC7/SPISSEL/P1.7

86

WR

82

RST_OUT

83

PSEN

84

RD

85

RD???

87

RST_IN

88

AGND

89

VREF

90

AVCC

91

RXD1/P3.0

92

TXD1/P3.1

93

INT0/P3.2

94

INT1/P3.3

95

90C7101

3400_USBD+

13

3400_USBD-

15

U1

90C7101

GND

1

PB5

2

PB4

3

PB3

4

PB2

5

PB1

6

PB0

7

PD2

8

PD1

9

PD0

10

PC7

11

PC6

12

PC5

13

PC4

14

Vcc

15

GND

16

PC3

17

PC2(VSTBY)

18

PC1

19

PC0

20

PA7

21

PA6

22

PA5

23

PA4

24

PA3

25

GND

26

PA2

27

PA1

28

PA0

29

AD0

30

AD1

31

AD2

32

AD3

33

AD4

34

AD5

35

AD6

36

AD7

37

Vcc

38

AD8

39

AD9

40

AD10

41

AD11

42

AD12

43

AD13

44

AD14

45

AD15

46

CNTL0

47

RESET

48

CNTL2

49

CNTL1

50

PB7

51

PB6

52

U2

PSD834F2V

7101_AD0

7101_AD1

7101_AD2

7101_AD3

7101_AD4

7101_AD5

7101_AD6

7101_AD7

7101_A8

7101_A9

7101_A10

7101_A11

7101_A12

7101_A13

7101_A14

7101_A15

7101_AD0

7101_AD1

7101_AD2

7101_AD3

7101_AD4

7101_AD5

7101_AD6

7101_AD7

7101_A8

7101_A9

7101_A10

7101_A11

7101_A12

7101_A13

PSD_A14

7101_A15

7101_PSEN

7101_ALE

7101_RD

7101_WR

7101_ALE

7101_WR

7101_RD

7101_PSEN

F_TDO

834TDO

F_TCK

F_TMS

7101ADC3

7101ADC2

7101UART0RXD

7101UART0TXD

7101ADC0

7101ADC1

F_TMS

F_TCK

F_TDI

834TDO

X2

7101RSTOUT7101RSTOUT

U1_AC1

0.1uF

7101ADC4

7101ADC5

7101ADC6

7101ADC7

X1

DVCC2

DVCC2

AVCC1

U2_C1

1u

U2_C2

0.01u

DVCC2

90C7101ADCVerificationBoard

32

VREF7101Clock

7101JTAG

JTAG

U1_AC2

10u

X1

7101RSTIN

RST_C

105P

12

43

RST_PB

SW_PB

RST_D

1N4148

7101RSTIN

RST_R

10k

U1_C2

0.1u

U1_C5

0.01u

5V

Vrx_C2

1u

Vrx_C1

100u

12

16

3

15

4

14

5

13

6

12

7

11

8

109

JP4

JPAIN_R1

300

JPAIN_C1

0.1u

RS232_TXD0

RS232_RXD0

R2out

9

R2in

8

T1in

11

R1out

12

T1out

14

R1in

13

T2in

10

T2out

7

C1+

1

C1-

3

C2+

4

C2-

5

V+

2

V-

6

VCC

16

GND

15

U8

ST3232

DVCC2

RS232InterfaceCircuit

RS232_TXD0

RS232_RXD0

DVCC2

7101UART0TXD

7101UART0RXD

7101UART0

U8_C1

0.1u

U8_C6

22u

U8_C5

0.1u

U8_C2

0.1u

U8_C3

0.1u

U8_C4

0.1u

U1_C1

4.7u

U1_C3

47u

DVCC1

1

2

3

JP_AIN

CON3ADC_IN1

ADC_IN2

AIN1_R1

1k

ADC_IN1

AVCC1

2

3

48

1

U9A

MAX4489

AVCC1

ADC_IN2

IN

1

GND

2

OUT

5

NC

3

NC

4

U3

MAX6129_EUK30-T

Analoginputoption1:

Fortestonly.

Analoginputoption2:

Low-noisevoltagefollower.

Low-noisevoltagereference.

Serialtype.

U8won'tbeassembleduntilboardno

U1_C4

1u

Vrx_L

1mH

AIN1_D

TS431-Z

AIN1_R2

3k

AIN1_R3

10k

AIN1_C2

0.1u

AIN1_C1

10u

Vrx_C3

0.01u

U8_R1

100

U1_R1

100

X1_R1

200

U2_C3

1u

U2_C4

0.01uPin8330083400

738P1.58P2.6

748P2.68P1.5

138NC8USB+

158NC8USB-

ADC5IN

12

34

JP2

HEADER2X2

ADC5IN

PSD_A147101_A14

7101ADC5

7101_VREF

1

2

3

JP_VREF

CON3

7101_VREF

AVCC1

VREF

F_TMS

F_TCK

F_TDI

F_TDO

DVCC2

FL_R

470

FL_D

RED

FL_C1

0.01u

JEN

1

TRST

2

GND

3

CNTL

4

TDI

5

TSTAT

6

VCC

7

RST

8

TMS

9

GND

10

TCK

11

GND

12

TDO

13

TERR

14

FLASH_LINK

7101RSTIN

DGND

DGND

DGND

DVCC2

FL_C2

1u

DVCC2

FL_R1

10k

FL_R2

10kFL_R3

10k

U1_R2

1.5k

DVCC1

VCC

4

GND

2

OSC_OUT

3

OE

1

X1

OSC

DVCC2

X1_C1

1u

X1_C2

0.01u

DVCC2

ChinaMMCC

DVCC2

U9_C

0.1u

AVCC1

TP_AGND

U9_R

5.1k

TP_ADCIN

1

6

2

7

3

8

4

9

5

J_UART

DVCC2

MCU,PSD

11/13

AN2010 - APPLICATION NOTE

Figure 9. 90C7101 ADC Verification Board Power Supply Schematic

AI10223

1234

A

B

C

D

4321

D

C

B

A

Title

NumberRevisionSize

A4

Date:8-Jun-2004Sheetof

File:D:\ww\Projects\Protel\VeriADC.ddbDrawnBy:

90C7101ADCVerificationBoard

33

SW1

SWITCH

Vin

3

GND

1

Vout

2

U5

LD1117-3.3V

U6_R

1K

U5_C3

100u

Vin

1

GND

2

Vout

3

U6

78M05-5V

U6_C1

220uF

D5

1N4004

U6_C3

0.01u

U5_C2

0.01u

J15V

5V

DVCC1

V_UNREG

U6_C2

100u

Vin

3

GND

1

Vout

2

U7

LD1117-3.3V5V

DVCC2

AVCC1

AV1_L

100uH

AV1_C2

1u

AV1_C1

100u

AV1_C3

0.01u

AGNDDGND

JP1_C2

0.01u

JP1_C3

1u

JP1_C4

100uF

U5_C4

1u

U6_C4

1u

U6_LED

RED

ChinaMMCC

1

2

3

JP1

CON3

TP_AGND0

CB1

TP_DGND1

PowerSupply

12/13

AN2010 - APPLICATION NOTE

REVISION HISTORY

Table 1. Document Revision History

Date Version Revision Details

15-Oct-2004 1.0 First Issue

13/13

AN2010 - APPLICATION NOTE

If you have any questions or suggestions concerning the matters raised in this document, please refer to the MPG

request support web page:

http://www.st.com/askmemory

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

) 2004 STMicroelectronics - All rights reserved

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