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Power mode technologies verify today's SoCs

Posted: 27 Feb 2008     Print Version  Bookmark and Share

Keywords:power architectures  system-on-chip  Power Definition Markup Language 

Five technologies—Power Definition Markup Language (PDML) specification, power-aware simulation, structural power checks, power-related assertions and formal analysis of the power control logic—provide outstanding checking and coverage while shaving half the power verification time. These technologies are the key components of an effective power verification methodology to ensure that low-power design produces high-confidence chips.

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