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New SiWare products roll out

Posted: 01 May 2008     Print Version  Bookmark and Share

Keywords:SoC  memory compiler  logic libraries  40 nm 

Virage Logic Corp. has released a new SiWare product portfolio that is claimed to enable SoCs to run faster, manage power more efficiently, use less area, and achieve higher manufacturing yields.

The new portfolio includes new memory compilers and logic libraries for TSMC's 40-nanometer (nm) physical IP for SoC design.

The SiWare product line, first released in October 2007 for the 65nm process, targets increasingly complex design requirements placed on physical IP at advanced process nodes. The company's Memory compilers and SiWare Logic libraries have a complete "dashboard" of options to effectively manage design trade-offs and meet specific requirements.

The 40nm SiWare, building from the earlier 65nm SiWare product line, includes advanced built-in power management capabilities that will enable designers to mitigate high power consumption at this advanced process node.

According to Rich Wawrzyniak, senior analyst at Semico Research, "The company's new 40nm SiWare offering shows attention to detail in terms of providing a built-in power management solution for SoC designers. With the ability to manage and optimise speed, power, area, and yield trade-offs, the robust SiWare products enable designers to successfully address the complex challenges of 40nm design."

Brani Buric, vice president of product marketing and strategic foundry relationships at Virage Logic, meanwhile, said, "Virage Logic's broad IP portfolio and extensive silicon validation program enables our customers to reduce design risk, shorten time-to-market and time-to-volume, and lower their development costs."

All SiWare memories are fully supported by Virage Logic's STAR Memory System, the company's flagship integrated embedded memory test and repair system.

The SiWare Logic product line includes yield-optimised standard cells for a wide variety of design applications at 40nm with multiple threshold process variants. SiWare Logic libraries are offered using three separate architectures to optimise circuits for Ultra-High-Density, High-Speed, or general use. SiWare Ultra-Low-Power extension libraries provide designers with the most advanced power management capabilities.

Primary end markets for SiWare IP on TSMC's 40G process include computer, graphics, networking and storage applications, while primary end markets for SiWare IP on TSMC's 40LP process include wireless, battery-operated and consumer applications.

SiWare Memory compilers and SiWare Logic libraries are available now for early adopters of TSMC's 40G and 40LP processes. Early partners already have internally qualified SiWare IP in silicon. Virage Logic's qualification process, based on advanced test chip methodologies, is in progress and will be finalised as early as July 2008. Project pricing starts at Rs.40.32 lakh ($100,000). The SiWare product portfolio supports all major electronic design automation (EDA) tool flows targeted for the 40nm process including Cadence Design Systems, Magma Design Automation and Synopsys.





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