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Synopsys 45nm certifies for USB 2.O PHY

Posted: 22 Apr 2008     Print Version  Bookmark and Share

Keywords:USB 2.0  45nm  low power  tuning circuits 

The new Synopsys USB 2.0 product was announced to be the first 45nm USB 2.0 PHY IP to be approved for Hi-Speed USB PHY certification by the USB Implementers Forum. According to the company, the USB 2.0 nanoPHY IP only uses half the power and die area in comparison with previous USB PHY IP solutions, enabling faster time-to-market with reduced risk.

The company offers the DesignWare USB 2.0 nanoPHY IP for a broad range of high-volume, mobile and consumer applications where the key requirements include minimal area and low power consumption. According to Synopsys, the IP addresses key requirements by implementing an architecture that provides a highly effective combination of small area, low power consumption and minimal leakage. In addition, the DesignWare USB 2.0 nanoPHY IP has unique built-in tuning circuits that enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations without the need to modify the existing design. This feature, says Synopsys, allows designers to increase yield and minimise the cost of expensive silicon re-spins.

The logo-certified DesignWare USB 2.0 nanoPHY IP for the 45nm process is available now. In addition, the USB 2.0 nanoPHY for the 40nm process is currently scheduled will be ready by 2H 08.





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