Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > Memory/Storage
 
 
Memory/Storage  

Changes delayed ST-Intel phase-change memory

Posted: 15 Feb 2008     Print Version  Bookmark and Share

Keywords:phase-change memory  ST-Intel JV  flash memory 

Researchers from Intel Corp. and STMicroelectronics could have produced samples of 128Mbit phase-change memories in 90nm process technology as early as June 2007 but opted instead to take time to improve the memory, according to Paolo Cappelletti, group VP for advanced technology development at ST's flash memory group.

In March 2007, Intel organised a teleconference in which Ed Doller, then chief technology officer of the flash memory group at Intel, told listeners that Intel was preparing to sample a 90nm 128Mbit phase-change memory to customers in 1H 07. Doller said at the time that he was hopeful the memory would go into volume production by the end of the 2007.

The phase-change memory is based on a thermally induced reversible change in a chalcogenide material—between an amorphous and crystalline state. The 128Mbit device has been designed as a pin-compatible NOR replacement that provides fast read and write speeds at lower power than conventional flash, and allows for the bit alterability normally seen in RAM.

Capelletti told EE Times that the 90nm non-volatile phase-change memory was delayed from that original prediction to help build a better foundation for a memory product at a more advanced manufacturing node.

During 1H 07, engineers working on the follow-on to the 90nm phase-change memory at an ST pilot line in Agrate, Italy, made some changes to the memory cell to improve integration, said Cappelletti. "We saved one critical mask, made the memory cell more scalable and changed the electrical distribution across the array."

"We were not yet in production so we decided to reproduce these changes in 90nm," said Cappelletti. He added that the decision was done to allow an easier transition from the 128Mbit 90nm memory to the next-generation. Cappelletti said he could not say whether that would be implemented in a 65nm process.

"We were able to produce the 90nm sample in Q4 07. The shipment happened in Q1 because we wanted to tie three events together: the delivery of samples; the ISSCC paper on multilevel-cell PCM and the demonstration in Barcelona," Cappelletti said.

The reference to the Mobile World Congress in Barcelona is believed to be a demonstration of the use of phase-change memory as a replacement for NOR flash memory within a mobile phone.

- Peter Clarke
EE Times Europe




Comment on "Changes delayed ST-Intel phase-chang..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top