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PCI-SIG enhances PCIe ver 2.0

Posted: 16 Jan 2007     Print Version  Bookmark and Share

Keywords:PCIe 2.0  PCI-SIG  interconnect 

The PCI Special Interest Group is making progress on a basket of feature extensions to its latest 2.0 specification, all of which should be available by June at the latest. The new features could enhance system performance as well as smooth a path for accelerators and storage devices riding the interconnect.

The enhancements include limited support for cache-coherent transactions as a way to synchronise traffic, particularly between host CPUs and co-processors, a new technique for handling virtual memory and support for multicasting. The SIG hopes to define these features—and perhaps others—as engineering change notices on top of PCIe ver 2.0 by April, although some items may not be completed until June.

The work "has really come together these past couple of months. Training on the concepts has started to the members to prep them for the spec reviews," said one source who asked not to be named.

"It's all incremental advances, but in certain markets they will be significant," said a second source who asked not to be named.

PCIe features
Chip interconnects represent a competitive arena where Intel Corp. and archrival Advanced Micro Devices Inc. are sparring. Intel is expected to use the enhancements to PCIe as the main route for third parties to link to its chipset and CPUs, competing with versions of HyperTransport used by AMD.

The multicast capability will let a PCIe switch blast one element of data to multiple end points, saving bandwidth and latency in some applications. The feature will be most useful in systems that use multiple graphics chips, or monitors, or systems with redundant or mirrored storage capabilities.

A number of the extensions bring some of the features of coherency to PCIe, creating a mainstream link between hosts and co-processors without all the complexity of a fully cache coherent interconnect. Although the SIG has not disclosed details yet, this appears to work by creating a coherency plane as a new abstraction level across which PCIe and a separate interconnect such as a processor bus can share information about transactions.

These new coherency-aware shared transactions can occur at the level of processors, chipset and I/O devices. At the I/O level, these transactions can help plug a hole in virtual memory subsystems so that needed data can be retrieved quickly, reducing latency.

The PCI-SIG forbids members to discuss details of proposals in progress. However, individual companies have publicly and privately disclosed parts of proposals they back.

For instance, Intel, IBM and other partners disclosed some of the work in 2006 under the name Geneseo. AMD made a public presentation about its virtual memory proposal for I/O page fault handling at the Windows Hardware Engineering Conference early this year. In the end, PCI-SIG will release work that has been developed and modified by a wide array of its members.

"Geneseo does not exist other than an Intel marketing term, and as a term it was never recognised by the PCI-SIG and is never used in any PCI-SIG discussions," said the first source. "All of the proposals have seen extensive discussion and modifications no matter the source of the proposal," he added.

Separately, work continues on ver 3.0 of PCIe announced in August that targets physical layer transfer rates up to 8GTransfers/second (GTps). A subcommittee working on modeling an encoding scheme for the new data rate has not yet settled on key signaling requirements such as equalisation and pre-emphasis, according to the second source.

The group must also define limits on jitter and crosstalk as well as a backward compatibility scheme. "It will take time for them to work all that out," he said.

The speed increase is not likely to emerge in products until 2010 or later. Some companies are still awaiting first silicon for PCIe chips based or ver 2.0, which has a theoretical physical layer data rate up to 5GTps.

Meanwhile, interest is on the rise from the communications sector for PCIe, which was originally designed primarily with the needs of computing in mind. "Even where [OEMs] are using backplane Ethernet, they are still considering Express as their local bus," said the second source.

An IEEE standard for backplane Ethernet defined at 1 and 10Gbit/s data rates is gaining traction, making it unlikely PCIe will become a backplane link for systems such as routers and switches. The IEEE standard defines longer distances and more connectors than in the PCIe spec, and it consumes as much as 2W per channel.

"You can't put several of those channels in an Express end point or switch," said the second source, suggesting a backplane version of PCIe might require 65nm process technology to meet such requirements.

He still held out hope PCIe may be used in backplanes for server blade designs, which typically need shorter distances and fewer connectors. However, enabling that use will require I/O virtualisation capabilities still in a late stage of being defined by the SIG, he said.

- Rick Merritt
EE Times




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