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High-k dielectric process for CMOS eliminates gate leakage

Posted: 06 Dec 2007     Print Version  Bookmark and Share

Keywords:high-k dielectric process  CMOS transistors  gate-leakage problem 

A high-k dielectric process for CMOS transistors promises to turn the International Technology Roadmap for Semiconductors into a freeway by eliminating the gate-leakage problem at advanced nodes down to 10nm.

Overheating due to excessive gate leakage is the number one hurdle to reaching advanced semiconductor nodes below 45nm. Now, a process with 1 million times less gate leakage could enable rapid migration to advanced nodes, according researchers at the Clemson University, South Carolina, U.S.

The rapid-thermal process of atomic layer deposition achieved an effective gate oxide thickness (EOT) of 0.39nm with only 10-12A/cm².

"This is a process that is robust and manufacturing tools could be developed for it without any fundamental barriers. We are using standard CVD techniques and the same precursors as everybody else," said Rajendra Singh, director of the Centre for Silicon Nanoelectronics at Clemson University. "The difference comes from our optimised process chemistry and our use of different kinds energy sources—that's what our patent covers."

As gate oxide thickness were slimmed for 45nm nodes and below, the industry has moved to using high-k dielectrics. For instance, Clemson's hafnium gate oxide high-k dielectric measured 2.4nm in thickness, but had an EOT of 0.39nm when compared to conventional silicon dioxide.

The semiconductor roadmap calls for high-k dielectrics at the 65nm node, but most manufacturers, including Intel Corp., have delayed going to high-K dielectrics until the 45nm node. The reason is that manufacturers would have to solve the problem of higher gate leakages through dielectrics that insulate less well than silicon dioxide.

Clemson's results indicate that such high-k dielectrics were the right way to go, and should take the industry down to the 10nm node.

"It has significant impact on the silicon IC manufacturing industry," said Singh. "Semiconductor manufacturers are currently debating whether it's worth the cost to change to larger 450mm wafers, but using our invention eliminates several processing steps resulting in an overall reduction in costs at advanced nodes."

- R. Colin Johnson
EE Times




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