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Mentor's place and route system tips ST's STB chip

Posted: 30 Nov 2007     Print Version  Bookmark and Share

Keywords:Olympus-SoC Mentor  STB chip STMicroelectronics 

STMicroelectronics has taped out an advanced process, multimillion-gate STB chip using the Mentor Graphics Corp.'s Olympus-SoC place and route system. The Olympus-SoC provides next-generation netlist-to-GDSII system that concurrently optimises for variations in design modes, process corners and manufacturing variations. It is targeted for high-end customers in wireless, handheld, graphics, STB, networking and processor application segments who are designing at advanced process nodes.

"We used Olympus-SoC to tape out an advanced STB chip containing 12 million gates and manufactured using an 80nm process," said Thierry Bauchon, R&D director, home entertainment & displays group, STMicroelectronics. "Although this is an extremely complex design with six modes and four corners of operation, we were able to complete the migration to the 80nm process in a fraction of the original three month schedule."

"The Olympus-SoC place and route system is quickly gaining momentum as designers replace their existing solutions to take advantage of our innovative architecture, high capacity data model, concurrent analysis and optimisation across multiple modes and corners, and litho-driven routing for their advanced process technologies," said Pravin Madhani, general manager for the place and route division at Mentor Graphics.




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