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FPGAs clear the serial backplane design hurdle

Posted: 16 Sep 2007     Print Version  Bookmark and Share

Keywords:serial backplane design  FPGA  serial I/O systems 

As system throughput requirements increase, the parallel backplane technologies of old will be displaced by Serdes-based backplane sub-systems that provide higher bandwidth, better signal integrity, lower EMI and power, and simpler PCB designs.

designing backplanes with high signal integrity is important. Also significant is the use of proper silicon ICs with Serdes technology, capable of driving backplanes with low BERs. Silicon-based approaches to mitigating signal integrity issues are particularly important in "legacy upgrade" scenarios, in which designers re-use older backplanes with legacy components and design rules. There are also challenges in developing serial backplane protocols and fabric interfaces. The majority of backplane designs leverage legacy ASICs, which have proprietary protocols. You can use off-the-shelf standards-based switch fabrics. This saves development time, but you must have silicon solutions that conform to the standard protocol, and the flexibility to customise the end product and make it unique.

This paper discusses how you can meet many of these challenges in serial backplane design, using FPGAs and IP solutions.

View the PDF document for more information.




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