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Cadence, SMIC jointly develop RF design solution

Posted: 06 Aug 2007     Print Version  Bookmark and Share

Keywords:RF design  wireless IC design  RFCMOS process 

Cadence Design Systems Inc. and Semiconductor Manufacturing International Corporation (SMIC) have collaborated to developed RF design solution and announced the availability of SMIC RFCMOS 180nm process design kit (PDK) that supports the Cadence RF Design Methodology Kit.

As part of their joint effort and to ensure widespread adoption, Cadence and SMIC will jointly host RF IC methodology workshops and provide RF kit applicability consulting to RF designers in China. RF design workshops are planned for Shanghai, Beijing and Shenzhen.

The new solution provides wireless chip designers in China access to the design software and methodologies necessary to achieve shorter, more predictable design cycles by helping to ensure that silicon performance matches design intent.

"We are excited about this jointly developed RF design solution that will help our mutual customers in China design and deliver high-quality RF devices," said Lee Yang, fellow of the RF Group at SMIC. "We have worked diligently with Cadence to provide this level of design capability to our customers, and we are continuing our close partnership with Cadence to develop RF IC solutions based on our 130nm and 90nm RFCMOS processes."

SMIC has been employing the RF design kit while working jointly on the National High-Technology Research and Development Program with two of China's leading institutes based on its own RFCMOS technology. SMIC is expecting to extend the development effort to 130nm and 90nm nodes as part of the Shanghai Innovation Initiative Programs for RF Core IP development.

The Cadence RF Design Methodology Kit includes an 802.11 b/g WLAN segment representative design, a full suite of block-, chip-, and system-level testbenches, simulation setups, test plans, and applicability consulting on the RF design and analysis methodologies. The kit focuses on top-down RF IC design and full-chip verification, and addresses behavioral modeling, circuit simulation, layout, parasitic extraction and re-simulation, and inductor synthesis. It also focuses on IC verification within a system context, leveraging system-level models and testbenches for use by designers in the IC environment.

"We are pleased with our joint work with SMIC, which results in improved quality and productivity in the design of RF devices for our mutual customers in the Chinese RF design market," said Craig Johnson, corporate VP of marketing at Cadence.




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