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ST unveils low-power 45nm CMOS platform

Posted: 15 Jun 2007     Print Version  Bookmark and Share

Keywords:45nm CMOS process  immersion lithography  design platform 

STMicroelectronics (ST) has wrapped off details of its 45nm CMOS design platform for next-generation SoC product development for low-power, wireless and portable consumer applications.

The company's low-power process option with multiple threshold transistors cuts the silicon area by half compared to designs implemented in 65nm technology. At the same time, the process improves speed by up to 20 per cent or reduces leakage current by half while in operation, and, in retention mode, reduces leakage current by several orders of magnitude. The latter option will bring important benefits to designers of portable products, where battery life is a significant factor.

The 45nm low-power CMOS platform has already been used to tape-out the design of a highly integrated 45nm demonstrator SoC device. This chip design includes an advanced dual-core CPU system and associated memory hierarchy, featuring low-power techniques required at the 45nm process technology node to combine new levels of performance with very low power consumption.

The new low-power design platform, which takes full advantage of the multiple features and modularity of 45nm process technology, was developed at the ST site in Crolles and verified at the 300mm wafer facility operated by the Crolles2 Alliance.

"Early access to low-power 45nm CMOS technology is crucial to industry-leading manufacturers in their development of new wireless and portable consumer products, especially for next-generation 3G and 4G handheld multi-media terminals," said Laurent Bosson, executive VP of manufacturing and technology R&D, ST. "The silicon developed using ST's low-power 45nm CMOS platform will enable applications to combine very high performance with low power consumption."

In common with other 45nm platforms being readied for deployment, ST's low-power 45nm process features all of the advanced modules required for high density and high performance. These important modules include 193nm immersion lithography for critical patterning layers; shallow-trench isolation and transistor stressors; advanced junction engineering, using millisecond anneal; and very low-k inter-metal copper dielectric, allowing reduced interconnect capacitances. In addition two cell libraries are available: one optimised for high performance and the other for low power consumption, giving designers a rich selections of options.

The 45nm design platform is fully supported by the CAD tools from Cadence, Mentor Graphics, Synopsys and Magma through design solutions that have been developed in partnership between.




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