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Renesas develops SOI SRAM tech for 32nm, beyond

Posted: 14 Jun 2007     Print Version  Bookmark and Share

Keywords:SOI technology  SRAM  32nm process node 

Renesas Technology Corp. has developed a new technology to implement on-chip silicon-on-insulator (SOI) SRAM in the 32nm node and finer processes. Through the newly developed technology, the Tokyo-based chipmaker hopes to extend operation margins by controlling the body potential of SRAM component transistors individually in line with SRAM operations such as writes and reads.

Test fabrication and evaluation using the technology on 2Mbit SRAMs in a 65nm CMOS process recorded an approximate 100mV improvement in operating lower-limit voltage. The read and right margins improved by 16 per cent and 20 per cent, respectively. There was also a 19-per cent reduction in transistor electrical characteristic variations.

There was a 27-per cent improvement in static noise margin in the 32nm generation simulation; it improved to 49 per cent at 22nm.

Renesas was to present the results of its experimental fabrication and evaluation at the 2007 Symposium on VLSI Technology in Japan this week.




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