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Low power challenges push for system-level EDA

Posted: 01 Jun 2007     Print Version  Bookmark and Share

Keywords:low-power design  Common Power Format  Unified Power Format  Cadence  Synopsys 

Facing mounting challenges of low-power design especially in complex mixed-signal SoC designs, designers are expecting a higher degree of system-level capability in EDA tools.

There are strong expectations from tools to analyse and optimise power at the architecture level, extend low-power design techniques for analogue/mixed-signal design and expand techniques for concurrent optimisation of power, area, and timing at the early stages of the design process. Growing concerns about the impact of power consumption on the system and packaging cost are also raising expectations of chip-board-package co-design capability from EDA tools.

Padmanabhan S.N.
Padmanabhan: Optimising power at the system level is a more holistic approach, and gives you maximum power conservation.
"If you are able to conserve or optimise power, then you can choose low-cost packages, which will reduce the cost of implementation and the bill of material (BOM) cost for the end-product," pointed out Padmanabhan S.N., senior VP – semiconductors, MindTree Consulting.

"At the advanced process nodes, dissipation of leakage power is significantly higher. Hence, the system-level design, the package design and board design become an important consideration," noted Mohit Bhatnagar, group marketing director, digital IC, Cadence Design Systems India Pvt Ltd.

A key driver that is fuelling the growing expectations is the critical importance of power management in contemporary SoC designs as they migrate to 65nm or lower process geometry. Power optimisation will also be a major aspect in large equipment that gets direct plug-in AC power, such as telecommunication switches and routers. Various environmental and regulatory agencies are beginning to enforce power constraints on equipment in their bid to foster the development of green equipment.

"Leakage is extremely important at 65nm and below, specially, but not only for portable wireless applications that have standby. For non-portable applications, the need to reduce power is driven by new regulatory standards and packaging costs," said Gal Hasson, director of marketing, RTL synthesis and low-power products, Synopsys Inc.

Design challenges
Techniques for low-power design are well established as far as the digital portions of mixed-signal SoCs are concerned. However, low-power techniques that work effectively for the analogue blocks of the design are yet to come into the mainstream.

"If you scale down from 90nm to 65nm in the digital domain, it is essential to drop the voltages as well due to the geometry related problem. However, the technology node does not scale well in the analogue space," Padmanabhan explained. "Techniques like voltage scaling can even have an adverse impact on power consumption of analogue blocks. The analogue portion can only tolerate voltage drop to a certain extent to maintain the level of precision. If you drop voltages below that level, then the power consumption actually goes up.

"EDA tools tend to treat analogue portions as another IP block or as a separate island that has its own voltage and other characteristics—that is the best that can be done as of today. We have to wait until a new methodology emerges," shared Padmanabhan.

Designers face serious challenges while deploying low-power design techniques in the digital portion of mixed-signal SoCs. The high degree of manual involvement in the design process impacts design productivity, and complete power optimisation is often a casualty.

As the low-power design entails accurate power estimation and analysis at each stage of the design flow, manual deployment impacts productivity and time-to-market considerations. Complete power optimisation is uncertain as designers often trade off power conservation considerations with the design project schedule.

Some of the low-power design techniques, such as voltage islands and multi-threshold gates, may adversely impact other performance considerations like silicon area. "Multi-threshold gates are a little complicated from a basic building block perspective as you need to have multiple elements. Maybe it is not feasible to have multi-threshold gates serving more than two voltages. This is because, practically then, these gates become larger, and they may create additional problems, such as area problems," said Padmanabhan.

EDA tool support
EDA tools from the major providers currently do support power optimisation in their tools. However, most tools seem to be focused more on supporting the circuit-level power conservation techniques, which enable designers to mainly control leakage current. The capability of EDA tools to accurately analyse power consumption at the RTL level is still emerging.

"To verify at the transistor level is time consuming. It is difficult to locate at the lower level of abstraction functional errors that have been caused by incorrect or un-optimised power management schemes. Secondly, if the design at the RTL level goes through any iteration, the power considerations have to be re-done," explained Mallikarjuna Bande, product manager—functional verification, Mentor Graphics.

"Optimising power at the system level is a more holistic approach, and gives you maximum power conservation. In contrast, circuit-level techniques tend to control one aspect of power conservation, for instance, optimising leakage current. Control of switching and other aspects are better addressed at the architecture level. If you go up the hierarchy, the power optimisation or conservation you get is higher," Padmanabhan observed.

Standard approach
The EDA industry's initiatives towards standardising power formats could create the conditions for EDA providers to address many of these designer concerns and provide users a holistic solution to power management.

The two initiatives—Common Power Format (CPF) and Unified Power Format (UPF)—provide a standards approach to express power intent and communicate the designer's power intent through the design, verification and implementation cycle. CPF was developed by Cadence, and is now being taken forward by the Silicon Integration Initiative (Si2). UPF, supported by Synopsys, Mentor Graphics and Magma Design Automation, was released as an Accellera standard in late February 2007.

An IEEE low-power study group—IEEE P1801—is attempting to converge the two formats into a single standard. In their future versions, both approaches intend to allow migration to higher levels of automation, leading to the availability of tools that provide users a way to define constraints, including power, at an early stage of design.

"We are really trying to enhance a better way of low-power automation and a better way of optimisation," said Dr. Chi Ping Hsu, corporate VP & chief strategist (products & technologies), Cadence Design Systems.

Designers expect the two power formats to converge into a single standard, driven by their need for compatibility between tools. The emergence of a single standard will facilitate interoperability of tools and dissolve any issue of incompatibility. This will allow designers to optimise their tool flow with a mix/match of tools from multiple EDA providers.

Pradip Dutta
Pradip Dutta: There will be much more movement in India towards a full line flow that standardises on a platform.
Pradip Dutta, managing director and president, Synopsys (India), however had a contrary view: "The 'point tool' approach is increasingly not working from the power optimisation standpoint. There will much more movement in India towards a full line flow that standardises on a platform."

It seems both logical and imminent that the power format standard will evolve to address the current gaps in low-power design—providing support for analogue and mixed-signal design and extending the scope of the format to the system level.

EDA R&D roadmap
The research roadmap of EDA providers is focused on strengthening power optimisation capability in EDA tools at the circuit and system levels. Companies are exploring ways to improve support for analogue and mixed-signal design. A research priority with two of the major EDA providers is the full-fledged support of power format standard across tools and flow solutions.

Synopsys' R&D roadmap focuses on leakage power reduction, and power design analysis and sign-off. Techniques for leakage power reduction include automatic power planning with MTCMOS and adaptive leakage optimisation (ALO). Design analysis and sign-off supports statistical power analysis to further drive timing/optimisation trade-offs.

Cadence is focused on increased system-level support for power optimisation, automation of dynamic voltage frequency scaling (DVFS) flow, automation of mixed-signal low-power flow, and support for silicon in package (SiP) co-design. Cadence is also extending verification capability to Palladium, its emulation hardware platform, whereby designers can run actual software on the platform, to get a more accurate estimation of power and verification.

Magma Design's research is concentrated on improved circuit-level techniques to control leakage and clock tree power. The particular areas of Magma's research focus are optimisation of leakage and dynamic power, and enhanced power distribution and sign-off analysis.

- Krishnan Sivaramakrishnan
  EE Times India




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