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TSMC plans 45nm wafers by Q3' 07

Posted: 16 May 2007     Print Version  Bookmark and Share

Keywords:45nm foundry race  fabrication techniques  accelerate 45nm process 

TSMC has announced its plan to release its first "commercial" 45nm wafers by September. The foundry service provider is accelerating ramp of its 45nm process despite the signs that the 45nm node could prove a painful and costly transition for foundry customers.

Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) had planned to in Q4, but is now shooting for September. Its first 45nm process is a low-power technology. Volume production is slated for 1H 2008.

The foundry giant's main rivals at 45nm—United Microelectronics Corp. (UMC) and IBM Corp.'s technology alliance—are not far behind and plan to ship their respective processes by year's end. IBM's foundry alliance partners are Chartered Semiconductor Manufacturing Pte Ltd and Samsung Electronics Co. Ltd.

It's unclear when—or if—other foundries will enter the 45nm race, though Fujitsu Ltd, Toshiba Corp., Semiconductor Manufacturing International Corp. (SMIC) and a few others are expected to field 45nm foundry processes.

For now, the question is whether the leading-edge foundries can deliver 45nm processes without hiccups. The shift from 90nm to 65nm went fairly smoothly, but some fear that the 45nm transition will bring back the nightmares of the 130nm node.

At 130nm, chipmakers introduced a slew of new technologies—such as copper interconnects and low-k—into the process flow. Foundries struggled to deliver chips on time.

Similarly, the 45nm node represents the first time that leading-edge foundries will use 193nm immersion lithography and ultra low-k dielectrics. Foundries are not expected to deploy high-k dielectrics or metal gates in the early stages of the node, however. High-k is still considered unproven for high-volume production.

45nm production schedule among leading foundries: Companies are running neck and neck.

"I don't think the challenges are any different for the foundries than they are for IDMs," said Dean Freeman, an analyst with Gartner Inc. "The move to immersion will create challenges. The same goes for low-k."

Costly mask
Another question is how quickly foundry customers will embrace 45nm. IC design costs alone will range between Rs.84.54 crore ($20 million) and Rs. 211.35 crore ($50 million). As for photomask costs, a "mask set" requires an outlay of Rs.2.11 crore ($500,000) to Rs.3.38 crore ($800,000) at the 90nm node and Rs.6.34 crore ($1.5 million) at the 65nm mode. At 45nm, photomask costs will be double the 65nm tally, said Naveed Sherwani, co-founder, president and chief executive of Open-Silicon Inc., a fabless ASIC house.

That won't deter all customers, Sherwani said, adding that he expects the 45nm node to be "driven by high-volume chipmakers like Xilinx, Intel and TI."

But many others won't jump on the bandwagon just yet, said Jack Browne, VP of marketing at MIPS Technologies Inc. Trailing-edge processes "are cheap," Browne said. "These processes will last a lot longer. There are a lot of small guys out there for whom Rs.4.23 crore ($1 million) is too much for a mask."

Acknowledging that fact, some foundries have offered an incremental migration path. TSMC recently rolled out a 55nm, half-node process, achieved with a die shrink of its 65nm technology.

The low-power 45nm process that TSMC plans to launch in September will be followed in 2008 by embedded memory, general-purpose, high-performance and RF derivatives. One key derivative will be a high-performance logic technology slated to roll Q2 next year, said Chuck Byers, director of brand management for TSMC.

"What you will see is a plethora of technologies," Byers said.

TSMC's 45nm process is said to offer two times the gate density of its 65nm process while cutting power consumption 30 per cent. The process is a 10-layer-metal technology with copper interconnects, strained silicon and a low-k film with a "k effective" rating of 2.5.

As it did for its 90nm and 65nm processes, TSMC will use a low-k film based on Applied Materials Inc.'s Black Diamond technology. It will also use ASML Holding NV's 193nm immersion tools.

Not far behind are IBM and its partners, Chartered and Samsung. Last year, the alliance announced plans to develop a 45nm process and ship it by yearend 2007. Like TSMC, the alliance partners will initially launch a low-power process.

The alliance claims to be on track for 45nm production. "We are prototyping silicon for customers at 45nm right now," said Steve Longoria, VP for the common platform technology at IBM. "We were a bit behind at the 65nm node, but at 45nm, we're running neck-and-neck with the leading foundries."

Market share for top 10 foundries: TSMC extends lead in area.

'Common platform'
The alliance is supposed to devise a "common platform" in which chips can be made and ported among the various member fabs with only one GDS-II file. There have been reports that the foundry vendors in the alliance are struggling with compatibility issues, but Longoria dismissed those rumors.

Even so, he acknowledged that the 45nm node presents challenges. For example, there are reports that the 193nm immersion tools require some hand holding in the fab, and that defects remain a problem. "There is a lot of fear, uncertainty and doubt about immersion," Longoria said, but "we're confident."

UMC, which has a similar timetable for 45nm, did not make an executive available for comment on the technology, but the world's second-largest foundry did release a statement to EE Times. "The move to 45nm, regardless of the application such as FPGAs or RF, poses a number of challenges," stated Chia Wen Liang, deputy director of the CRD Logic division and head of 45nm development at UMC. "New fabrication techniques often result in defect issues. For example, UMC's fabrication of working 45nm SRAMs encountered defect issues associated with immersion lithography, including resist/topcoat selection."

Further, "since traditional device-scaling methods can no longer be applied, due to the physical limitation of gate dielectrics material, many mobility enhancement techniques have to be introduced in this node, such as SiGe, compressive and tensile nitride films and stress memory effects for poly gates," the UMC technologist stated. "New integration schemes, new materials and new tools have dramatically increased the complexity of the 45nm process."

That very complexity means the 45nm foundry race is far from over, said IBM's Longoria. While the first crop of foundry adopters plans to ramp 45nm processes by year's end, "it's going to come down to execution" in September, he said.

- Mark LaPedus
EE Times




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