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Signal-integrity issues trouble multi-gigahertz era

Posted: 16 Mar 2007     Print Version  Bookmark and Share

Keywords:signal integrity  EDA  EDA tool  Serdes  interconnect 

Engineers want a new bag of tricks to manage signal integrity (SI) as data rates soar into multi-gigahertz territory.

As today's systems press towards 6Gbps serial interconnects, they face so much signal loss and distortion that they can no longer be designed or tested using conventional methods. Power and interference issues are creating other potholes.

The problems will only get worse. Engineers are beginning to implement PCIe 2.0, which operates at 5GHz, and they are discussing a 3.0 standard that could hit 8-, 10- or 12GHz. The Fibre Channel community is already working on an 8Gbps version, and the IEEE is studying a next generation of Ethernet that could hit 100Gbps.

"Three things that were once independent issues are coming together—signal integrity, power integrity and EMC," said Istvan Novak, an SI staff engineer from Sun Microsystems Inc. who chaired two panels at DesignCon. "Now, it's all one big mess that we have to sort out, and most of the time we don't have sufficient data."

Pushing speed limits
"A couple of years ago, we saw Serdes serial transceiver chips coming on and thought they would be easy to design," said Ian Dodd, an architect for high-speed tools in the board division of Mentor Graphics Corp. "Now we see problems with the weave of materials in the board. Meanwhile, people are pushing Serdes to their limits, creating more problems with the materials and power supplies."

In this environment, chip- and board makers are calling for a standard approach to signal integrity. The standard would replace separate, sometimes conflicting SI test procedures written into the specifications for interconnects such as PCIe, Fibre Channel, Infiniband and fully buffered DIMMs.

"Right now, it's not only handled differently for each standard, but every company in each standards group has its own approach," said Bryan Casper, who manages a signal research lab in the corporate technology group at Intel Corp.

A groundswell is building for an ad hoc group to establish a standard that could later be taken to a formal standards body, said Terry Morris, a fellow in Hewlett-Packard Co.'s server group.

The standard will likely be implemented in vector network analysers and involve highly skilled probe techniques, Morris said. Driving the need are problems with signal loss cropping up in mainstream boards, many of which are made in China, he added.

Equalisation techniques
A separate effort hopes to define a standard way to test high-speed transceivers. The chips use a variety of often proprietary equalisation techniques to send fast serial signals across a board, even when distortion keeps conventional oscilloscopes from verifying the signal.

"By the time the signal gets to the receiver, there's nothing we can measure for compliance. We have nothing to validate against," said Todd Westerhoff, VP of software products at Signal Integrity Software Inc.

Today, chipmakers create their own transceiver models, often using homegrown software. That prevents OEMs from modelling high-speed interconnects using chips from multiple vendors.

Cadence Design Systems Inc. is trying to rally industry support around a proposal for a standard API that would let EDA tools and test gear interrogate transceivers. At last January's DesignCon, Cadence showed a version of its Allegro PCD SI GXL tool using the API to display an accurate signal "eye" from an IBM 6Gbit Serdes without knowing the details of its proprietary equalisation scheme. The approach could also be used on an oscilloscope.

"You are looking at the eye inside the receiver chip," said Donald Telian, an SI consultant who helped design Cadence's first SI tools. "This is a first, to have the EDA tool and a tester share functionality like this."

The Cadence approach requires that chipmakers deliver an executable file in the form of a dynamic link library that lets a tool interrogate the chip for signal data. The queries do not reveal the proprietary equalisation approach the chip uses.

Power-reduction techniques
Separately, techniques to reduce power consumption for interconnects are expected to require multiple industry standards that are quietly in the works. The work requires collaboration among circuit, chip and board designers.

Engineers see 1mW/Gbps as the holy grail. Rambus Inc. is expected to plough new ground with a technique that claims to deliver I/O at as little as 2mW/Gbps.

Intel engineers claim techniques that hit as little as 10mW/Gbps. Mainstream PCs using PCIe links typically deliver I/O at 15-30mW/Gbps today.

Brian Kirk, an SI engineer from Amphenol TCS, showed a backplane that could carry 20Gbps signals, based on extrapolating techniques from the IEEE 802.3ap standard for 10Gbit backplane Ethernet. The Amphenol backplane used a plated through-hole design, advanced shielding to reduce crosstalk and differential connectors to compensate for skew. The design was based on a 16-layer FR4 board that did not go below 24dB in SNR.

"Our goal was to design a system without exotic materials or manufacturing processes," said Kirk. "We do feel the infrastructure to get to 20Gbps is available."

20Gbps signals
Separately, Cathy Ye Liu, a principal engineer who leads the high-speed Serdes team at LSI Logic Corp., laid out the trade-offs among a variety of signalling and equalisation schemes at data rates ranging up to 25Gbps.

Serdes chips typically double in data rate with every new process node. The availability of 65nm technology this year will open the door to 12Gbit Serdes, with 25Gbit transceivers arriving with the 45nm node, she said.

Liu described a hybrid equaliser that used a combination of techniques borrowed from linear- and decision-feedback devices to get a balance of lower power and high performance, which neither technique could achieve on its own.

In terms of signalling techniques, non-return to zero is best for rates below 12Gbits, but four-level pulse-amplitude modulation (PAM4) is better—though far from perfect—for rates reaching up to 25Gbits, she said. "We need to do something to reduce crosstalk" with PAM4 at 25Gbps, said Liu.

The fast Serdes could be used in bundles of four to power the next-gen Ethernet devices now being defined. They could aim for data rates as high as 100Gbps.

- Rick Merritt
EE Times




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