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EDA/IP  

SystemVerilog fails to deliver on design

Posted: 21 Feb 2007     Print Version  Bookmark and Share

Keywords:SystemVerilog  EDA  verification  verification language  design 

The full-court marketing push by major EDA vendors on behalf of the SystemVerilog language is working—but not as expected. Although the unified design and verification language is widely applied to verification, design use lags because of concerns about tool support.

SystemVerilog adds assertions, testbench generation and design language constructs to Verilog, the most widely used HDL for IC design. EDA vendor investment in SystemVerilog, which became the IEEE 1800 standard in late 2005, is huge. According to the Accellera standards organisation, 136 vendors will offer more than 350 SystemVerilog products this year compared with six vendors and nine products in 2004 when SystemVerilog 3.1a became an Accellera standard.

Estimates of the number of Verilog users who have stepped up to SystemVerilog range anywhere from 20 to 50 per cent, but one point of agreement is that the most commonly used SystemVerilog feature is assertions, next is testbench constructs. Falling well behind is design, where SystemVerilog adds a number of constructs that let designers work at a higher level of abstraction. Adoption of the design feature, however, has been hampered by the less than 100 per cent language support for those constructs.

"I thought designers would pick it up first, but they're a little more cautious about it," said Cliff Cummings, president of the training firm Sunburst Design Inc. and a contributor to SystemVerilog. Verification engineers, he conceded, need only a simulator to use SystemVerilog, while designers require synthesis, simulation and linting tools.

"On the design side, several tools are involved, and they all have to support the same SystemVerilog constructs for you to use them," said Stu Sutherland, president of training firm Sutherland HDL. "Today, different tools have implemented different portions of SystemVerilog, so it's very hard to do design."

While the primary usage of SystemVerilog today is assertions, it's actually the hardest part of SystemVerilog to learn because it involves a specialised assertion language, Sutherland said. Design constructs, on the other hand, have a "very minimal" learning curve, he said.

Analyst Gary Smith, president of Gary Smith EDA, estimates that SystemVerilog penetration is about 35 per cent. "The overwhelming reason for adoption is its assertions capability," he said. SystemVerilog is supplanting Synopsys Inc.'s Vera verification language, but not Cadence Design Systems Inc.'s "e," which Smith views as a higher-level language.

- Richard Goering
  EE Times




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