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Next-gen memory in the limelight

Posted: 02 Feb 2007     Print Version  Bookmark and Share

Keywords:DRAM  memory  flash  NOR flash  NAND 

The frantic search for a next-generation memory technology took centre stage at the IEEE International Electron Devices Meeting in December, amid growing concerns that DRAM and flash parts will no longer scale in the near future.

Chipmakers presented a dizzying array of next-generation or "universal memory" technologies, many of which claim to be the successors to DRAM and flash.

Simply put, the next-generation memory market is up for grabs. It is still unclear which technology will win the potentially huge universal-memory business, one that could reach Rs.3,45,791.60 crore ($76.3 billion) by 2019, according to iSuppli Corp. Cost and manufacturing issues will keep most of the also-rans from mainstream applications.

The vast majority will remain "paper tigers," said Frankie Roohparvar, VP of NAND development at Micron Technology Inc.

Still, there is an urgency to find a new memory solution, remarked Chang-Gyu Hwang, president and chief executive for the semiconductor business division at Samsung. That company's latest DRAMs and NAND flash parts are built around 50nm and 40nm processes, respectively. But current DRAM and flash technologies face various scaling roadblocks in the dreaded "deep nanoscale" era, which falls at the 20nm node and beyond, Hwang said.

"There is a growing concern about whether semiconductor technology can continue to keep pace with demand when silicon technology enters the deep-nanoscale era,'' he said. "There are ultimate limits to transistor scaling, and narrowing margins in manufacturing due to ever-increasing fabrication costs. Though most experts believe silicon technology will maintain its leadership down to 20nm, beyond this node, a number of fundamental and application-specific obstacles will prevent further shrinkage.''

Even today's memory devices are hitting the wall to some degree. For example, DRAM vendors, in tandem with their logic counterparts, have attempted to double the density of their products every 18 months. Vendors have announced parts based on 50nm processes. "Beyond 50nm, we may need another breakthrough for array transistors in DRAM," Hwang noted. Samsung is working on a body-tied, fin-shaped FET, or FinFET, that could take the DRAM down to 30nm, he said.

There are similar issues in flash, especially NAND. But in fact, NAND vendors are moving faster than Moore's Law by doubling their product densities every year, said Roohparvar. This has created a major disconnect between NAND vendors and their lithography tool suppliers, especially for production at the 50nm "half-pitch" node and beyond.

"We are ready to go to the market, but the equipment suppliers are not ready to supply us," Roohparvar said.

40nm geometries
Equipment makers ASML Holding NV and Nikon Corp. have separately shipped 193nm immersion lithography tools, which promise to process chips at geometries down to 40nm. But chipmakers are still scrambling—if not struggling—to get these newfangled and costly scanners into production, experts said.

However, scaling remains perhaps the biggest challenge for flash vendors. The floating-gate structure is the key component of traditional NOR and NAND devices, but many wonder just how long the technology will scale before running out of gas.

Been-Jon Woo, director of flash technology integration at Intel Corp., suggests that the floating-gate structure will extend at least to the end of this decade. "After that, we will have to make some major changes," Woo said.

One company has already moved to scale NAND. In September, Samsung trotted out a 32Gbit NAND chip made on 40nm process technology that eliminates the floating-gate structure. Instead, it sports a proprietary oxide-nitride-oxide layer that the company calls charge trap flash. Samsung claims this technique will allow it to more easily scale NAND down to the 20nm node.

Other technologies will also vie for dominance in next-generation non-volatile memory. There are three basic candidates: FeRAM, MRAM and so-called phase-change technologies.

Products based on MRAM and FeRAM have been introduced to the market, but they will remain niche-oriented, SRAM-replacement parts for the foreseeable future, Roohparvar said.

Several companies claimed major breakthroughs in phase-change memory, although these efforts are still in the R&D stage. In one effort, the team of IBM, Macronix and Qimonda AG said they had developed a reliable phase-change memory prototype that switches more than 500 times faster than traditional flash memory technologies. The device, which measures a minuscule 3-by-20nm in cross-section, is said to use less than half the power to write data into a cell, according to the companies.

At its heart is a tiny chunk of a semiconductor alloy that can be changed between an ordered, crystalline phase and a disordered, amorphous phase. The new memory material is a germanium antimony alloy to which small amounts of other elements have been added to enhance its properties.

Advanced MCUs
Taking another approach, Hitachi Ltd and Renesas Technology Corp. reported a refinement in their ongoing efforts to develop a phase-change memory technology. The novelty of the design lies in its use of an interfacial layer of tantalum pentoxide between the plug that connects to a MOS transistor and the phase-change film, which is a standard germanium antimony tellurium chalcogenide alloy. The technology will enable a new class of advanced MCUs, according to Renesas and Hitachi.

Samsung presented more details on another type of phase-change memory, dubbed phase-change RAM, or PRAM. Samsung said it has developed a working 512Mbit PRAM based on a 90nm process.

Geared as an eventual replacement for NOR flash, PRAM is similar to the technology used in CDs and CD drives. In a PRAM, an electrical current heats a chalcogenide film to either a crystalline or an amorphous state, each with very different electrical resistivity. This allows the two states to be read as a 0 or 1.

Samsung also moved in a completely different direction by combining today's NAND technology with 3D stacking techniques. The company has demonstrated an ultradense flash memory device by stacking 32bit NAND cell arrays or structures on top of each other with 63nm dimensions.

This is done by implementing a single-crystal-layer stacking technology. The NAND cell arrays are formed on the interlayer dielectric, thereby doubling the density without increasing the chip size. The technology is said to scale beyond the 30nm node.

Memory vendors, in fact, must pursue several avenues to find the right technology, Samsung's Hwang said. "These solutions will include not only 3D technologies, but also non-silicon technologies on a molecular scale," he concluded.

- Mark LaPedus
EE Times




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