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Cadence develops 'first' complete low-power solution

Posted: 02 Feb 2007     Print Version  Bookmark and Share

Keywords:Cadence  low-power  integrated flow  logic design  common power format 

Cadence Design Systems Inc. has announced that it has developed a low-power solution, the industry's first fully integrated flow for logic design, verification and implementation of low-power chips.

This solution integrates leading-edge design, verification and implementation technology with the common power format (CPF), an Si2 format for specifying power-saving techniques early in the design process, to deliver an end-to-end low-power design solution to IC engineers.

By preserving low-power design intent throughout the design, the solution eliminates manual labour, reduces power-related chip failure and provides power predictability early in the design process.

"This is a dramatic step forward for designers seeking low-power design capabilities. The solution is the first to provide designers with the ability to automatically use low-power techniques at the register-transfer level (RTL) using a common format, with the assurance they will function correctly throughout the verification, front-end and physical-implementation steps," Cadence vice-president Chi-Ping Hsu said in the statement.

The move to integrated, high-performance sub-90nm silicon creates heat-management challenges, which require power optimisation throughout the chip. Large end-product applications such as server farms require power optimisation at every level to reduce energy consumption. Similarly, cost considerations related to packaging are driving designers towards low-power design.

To meet these diverse requirements, designers are employing advanced low-power design styles such as power shut-off (PSO), multi-supply voltages (MSV) and state-retention power gating (SRPG). Automation of these techniques has been fragmented, with different tools using different ways of representing low-power intent.

As a result, designers have been forced to specify low-power functionality through a set of ad-hoc methods, causing power data to be entered manually, multiple times in a single design effort. This repetitious data entry is tedious, error-prone and makes predictability and verification of the design difficult.

The solution enables an entire multi-specialist project team to work from a common view of the design, which includes the low-power intent. It also improves design predictability and minimises the risk of chip failure.

CPF 1.0 has undergone comprehensive review by power forward initiative (PFI) advisors who are leaders representing all segments of the electronics industry, including semiconductor, foundry, semiconductor equipment, systems and electronic design automation companies.

PFI advisors provided over 500 inputs for incorporation into CPF 1.0, which was contributed to the Si2 low-power coalition in late 2006.

"This announcement demonstrates the wide applicability of CPF across low-power flows and highlights the potential for interoperability among diverse tools from one or multiple vendors," said Si2 CEO Steve Schulz.

As a Cadence project Torino milestone, the low-power solution is currently available and is scheduled to incorporate power-aware flow support for technologies in the current year.

- Gulab Chand
  EE Times India




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