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IBM finds way to quintuple heat dissipation power of chips

Posted: 18 Dec 2006     Print Version  Bookmark and Share

Keywords:IBM  Jet Array Cooler  vias  system design  thermal conductivity 

Thermal power management dominates high-performance system design today because the faster the chip, the more heat it produces. Air-cooled chips can now accommodate only about 12W/inch². But IBM Zurich Research Laboratory said it has found a way to double or even quintuple that number.

The lab showed two high-thermal-conductivity manifolds for future chips during the October BroadGroup Power and Cooling Summit in London. One manifold—the High Thermal Conductivity Interface—doubles the thermal power dissipation of air-cooled chips to 24W/inch². A second, water-cooled manifold—the Jet Array Cooler—takes the thermal power management of next-generation chips to nearly 60W/inch²—five times the power dissipation of air-cooled chips today.

"We are always looking for ways to cool chips more efficiently, so that our designers can optimise our chips for high performance, which is always a trade-off against power dissipation," said Dave Seeger, senior manager for electronic and optical packaging at IBM's T.J. Watson Research Centre. "Using the latest manifolds from our Zurich Research Laboratory, we should be able to air-cool future chips twice as well."

Today's air-cooled chips dissipate heat by way of metal heat sinks attached to the metal chip cap by a thermally conductive paste. Attaching a heat sink directly to a chip would produce small air gaps that function as thermal insulators—like double-paned glass. Designers use paste to fill in those gaps. The problem comes in attempting to tighten down the heat sink—the paste has no place to go.

Now the IBM technique has given it "a place to go that enhances thermal conductivity," Seeger said.

The scheme carves grooves hundreds of microns wide and deep into the metal chip cap, creating a manifold whose surface area—and, thus, its heat-dissipating capabilities—is greatly multiplied. By tightening the heat sink to only half the former pressure, the paste is thinned out to just 10μm thick.

"With our high-thermal-conductivity interface, we can get to thinner paste at lower pressures," said Seeger. "We have given the paste someplace to go—now we only need half the pressure to get twice the thermal conductivity."

The air-cooled manifold is only the first step in a hierarchy of thermal-power-management manifolds reported on at the summit by the originator of the concept, Bruno Michel, manager of the advanced thermal-packaging research group at IBM's Zurich lab. The next step is to expand the hierarchy of manifolds, starting with replacing the bottom side of the chip cap—where it interfaces with the chip—with 50,000 water jets, half of which squirt and half of which suck.

Into the groove

"Ours is the only approach that doesn't just bathe the middle of the chip with cool water and draw off the heated water on the sides," said Seeger. "Ours pulls hot water out right next to where cold water was injected, which is much more thermally efficient."

The liquid-cooled version will also have hierarchies of grooved manifolds between chips and their heat sinks, a setup akin to the hierarchies of caches between a modern microprocessor and its RAM. Following the liquid layer, which removes heat with thousands of 30μm- to 50μm-diameter jets on a 200μm pitch, is a 325μm-pitch manifold that connects to a layer of interlevel vias, directing the water either away from or down to the chip. The final layer is a top manifold with a pitch of 700μm.

"The entirely closed system uses a hierarchy of treelike branches to dissipate heat in the same efficient manner as natural systems," said Seeger.

IBM predicts these elaborate cooling hierarchies will be necessary for the fastest microprocessors used in future servers and scientific computers.

- R. Colin Johnson
EE Times




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