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Xilinx releases logic design solution for Virtex-5 LXT platform

Posted: 21 Nov 2006     Print Version  Bookmark and Share

Keywords:Xilinx  logic design solution  Integrated Software Environment  ISE  Virtex-5 LXT Platform FPGAs 

Xilinx Inc. has released a complete logic design solution including an update to its Integrated Software Environment (ISE) design tools for their latest Virtex-5 LXT Platform FPGAs, the first FPGA to deliver hard-coded PCI Express End-Point and Tri-mode Ethernet Media Access Controller (MAC) blocks. ISE 8.2i delivers a unique integrated timing closure environment and productivity-enhancing features, allowing users to fully exploit the connectivity, performance and power advantages of the Virtex-5 LXT family. Updated tools include the latest service packs of the 8.2i versions of ISE Foundation, ChipScope Pro, and PlanAhead Design and Analysis Tool.

ISE 8.2i provides an implementation environment to leverage the superior routing architecture of the Virtex-5 family and enhanced diagonal routing which supports block-to-block connectivity with minimal hops. The release provides access to the many features of the Virtex-5 LXT including the industry's lowest power 65nm transceiver, typically using less than 100mW per channel at 3.2Gbps.

The feature set of the ISE 8.2i design suite enables designers using Virtex-5 LXT devices to meet performance goals with greater certainty and reach design closure in less time. Xilinx users can maintain industry leading performance in even the largest FPGA design. With its unique Fmax technology, ISE delivers features such as next-generation physical synthesis with pre and post routing optimisation for Virtex-5 LXT designs. Enhanced physical synthesis support for the ExpressFabric technology reduces levels of logic and signal delay while packing designs more efficiently.

ISE Foundation 8.2i: Xilinx flagship design environment delivers a complete, front-to-back design solution. ISE Foundation 8.2i includes an integrated timing closure environment offering tighter correlation between logical and physical design domains. Automated cross-probing between constraint entry, timing analysis, floor-planning and implementation reports provides greater visibility and more efficient method for timing closure and debugging designs.

ChipScope Pro 8.2i: Enables on-chip debug at or near operating system speed. Available as an add-on option, the ChipScope Pro 8.2i solution reduces verification cycles by up to 50 per cent. ChipScope Pro 8.2i users can now take advantage of on-chip verification for designs which take advantage of the integrated PCIe block of the Virtex-5 LXT family of Platform FPGAs.




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