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Intel, AMD clash on defining interconnects

Posted: 16 Nov 2006     Print Version  Bookmark and Share

Keywords:AMD  Advanced Micro Devices  Intel  interconnects  multicore processors 

A battle royal is shaping up as Advanced Micro Devices Inc. (AMD) and Intel Corp. race to define interconnects for their next-generation multicore processors. The archrivals hope to use those links to weave separate webs of partnerships that will be keys to success in tomorrow's computer industry.

In late September, a group of chip and systems makers led by Intel and IBM Corp. launched Geneseo, codename for a set of extensions to PCI Express that aim to help graphics chips and other accelerators plug directly into a coherent processor. The news came in the wake of AMD's June announcement that it would invite the industry to plug into its proprietary HyperTransport CPU bus as part of a new program dubbed Torrenza.

The interconnects are likely to become part of the secret sauce for both companies' future multicore architectures. The extent to which the two are able to court the industry to provide blocks that may plug into 16 (or more) core CPUs could be a make-or-break factor in the two companies' turf wars in 2010 and beyond.

Extending Express
The Geneseo proposals aim to extend Express in four broad areas, providing fine-grained power management, a locking mechanism for shared memory, hints to help a coherent processor handle I/O more effectively, and memory and protocol efficiencies for mapping virtual to physical memory. The group may develop additional proposals in the future.

The resulting improvements fall short of creating a cache-coherent version of Express; as such, they do not provide all the underpinnings offered by the coherent HyperTransport (cHT) technology at the heart of AMD's Torrenza program. Nevertheless, functionally, the Express extensions aim to address many of the same core uses as Torrenza, including providing a standard connection between a processor and accelerators for functions that could include networking and XML processing.

In that sense, a big part of the motivation for Geneseo is stealing the wind from AMD's sails as the latter tries to capture interest from third-party chipmakers and OEMs.

Separately, Intel announced it has licensed its front-side bus (FSB) to both Altera Corp. and Xilinx Inc., so they can build FPGAs that link directly to Intel CPUs for a variety of high-performance computing applications. AMD earlier this year announced it was working with Altera and a handful of smaller companies on a similar plan with cHT.

Eventually, Intel is expected to migrate its FSB to a new link called Coherent Scalable Interconnect. CSI could include many constructs that Intel hopes the industry will adopt as part of the new Express extensions.

No one solution
The AMD and Intel approaches to linking other processors and cores to their CPUs could coexist, said Ivo Bolsens, chief technology officer for Xilinx, which hopes to work with both companies. "There's no one solution that is the final answer to everything," said Bolsens.

Marty Seyer, senior VP of AMD's commercial division, took a conciliatory view of the news. "We see multiple levels of coprocessing, ranging from this latest proposed PCI Express approach to the ultimate of direct connect into HyperTransport. AMD supports them all, as long as they drive open innovation."

The industry would love to see Intel and AMD get together to rationalise differences between their CPU buses, but few expect that to happen.

Bolsens described Intel's FSB coherency approach as superior to AMD's. "AMD relies on a distributed coherency model. There are significant differences between how you program that vs. the Intel FSB model, which people are more used to and is easier to program," Bolsens said.

Long-term scenario
By tapping Express, an open standard managed by the PCI Special Interest Group, Intel is reaching out to a broader community of companies than those using cHT, which is proprietary to AMD.

On the other hand, cHT will offer lower latency, greater bandwidth and full coherence—capabilities beyond Geneseo. That will give a performance boost to applications based on processing large databases or large graphics images.

Long term, the Geneseo and cHT concepts will likely be baked into Intel and AMD CPU architectures that accommodate eight, 16 and more cores. The CPU makers could then encourage chipmakers to provide their silicon as cores to give unique added value to their host processors.

A 2x4 debate
On the surface at last September's Intel Developer Forum, the battle seemed to be all about who is first to pack more cores on a chip. Intel said it will have four in November. AMD said it will have four—more elegantly done—probably in June.

Intel laid out plans for a line of quad-core desktop and server CPUs. They all put two dual-core dice in a single multichip module. The approach helps Intel get to market quickly while saving the cost of doing all-new silicon designs. But it limits performance gains, especially when one core needs to go off-chip and through a separate memory controller to access a core on the other die.

AMD's cores have three cHT interconnects and a memory controller on board, so all four cores will be able to talk to each other without going off-chip.

Chief executive Paul Otellini reacted to a reporter who called Intel's approach into question at a Q&A session at the forum. "Our initial quad-core CPUs are multichip modules, but so what? You guys are misreading the market if you think people care what's inside the package," Otellini said. "They just care about delivered performance."

The end is near
The fact is, both companies are near a dead end with the architectures they have today. Both are working in the labs on radically new architectures that will help them scale to eight, 16, 32 and more cores in the future. And both need significant industry support for their multicore plans if they are to succeed.

Intel says it is planning a CPU microarchitecture called Nehalem for its 45nm process, which will start production in two fabs in the second half of 2007 and a third fab by 2008. "In the 45nm generation, I would expect us to have monolithic quad-core designs, and after that, we will review what to do in the future," said Stephen Smith, director of desktop platforms at Intel.

It's likely Intel will try to leapfrog AMD by delivering an on-chip multicore architecture for Nehalem that accommodates at least eight cores, if not more. But Insight64's Brookwood said Intel probably will not have Nehalem chips available until mid-2008, because it typically debugs a new process with an existing architecture before shifting to a fresh design.

It's possible Intel has a more-aggressive plan for Nehalem. Intel researchers are working on as many as 100 projects for CPUs with 32 and more cores, and they're targeting 45nm process technology, said Joseph Schutz, director of the company's microprocessor lab.

More ambitious
One scenario envisions the Geneseo extensions to Express making their way into products sometime in mid-2008, about the time Nehalem chips hit. Then the follow-on architecture, called Gesiter, would likely introduce a more-ambitious multicore architecture, using some of the Geneseo constructs, for chips made in Intel's 32nm process.

Intel's Schutz said he foresees an architecture using highly streamlined X86 cores with a mix of local and shared caches. His group has developed several advances geared for multicore chips, including caching improvements, hardware thread scheduling and new instructions. The techniques milk significantly more performance out of multicore chips, he said, especially at 16-core and higher levels, where performance scaling drops off.

"We are transferring some of these techniques to product groups," said one Intel spokesman at IDF.

- Rick Merritt
EE Times

- Dave Bursky contributed to this report.




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