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NXP ref designs enable hybrid HD LCD TVs

Posted: 11 Sep 2006     Print Version  Bookmark and Share

Keywords:NXP  Nexperia  TV520/32  TV507  reference designs 

NXP, the independent semiconductor company founded by Philips, has announced two new TV reference designs: Nexperia TV520/32 for DVB/PAL and Nexperia TV507 for analogue TVs. Both designs are based on a silicon platform that enables TV manufacturers to develop hybrid digital and analogue LCD TV sets.

With the TV520/32 for DVB/PAL and the earlier introduced TV520/30 and TV520/20 for ATSC, NXP is now able to offer one hybrid platform for all regions worldwide. The TV507 is based on the same platform and offers the analogue-only version, thus enabling NXP's customers to spin off an analogue-only product from the same platform investment. All members of the family are pin-to-pin compatible, which means TV designers can re-use the investments across a range of products.

Set makers profit from reduced development costs, easy design-in processes and shorter lead times. With its unique features, NXP said TV520 platform allows customers to develop a product and bring it to market in as little as three months. Consumers benefit from having a uniform user interface for analogue as well as digital channels. Furthermore, TV507 promises a new, brilliant viewing experience as best-in-class picture quality can be offered at an affordable price point, the company said.

"Our solution is unique as it is based on one silicon platform serving the two worlds of digital and analogue TV sets. It is cost-effective and efficient for manufacturers to only work with one platform and offer two different end products with high picture quality," said Jos Klippert, marketing director, Digital TV solutions, NXP. "As more High Definition TV content becomes available, consumers are seeking LCD TVs that offer the highest quality analogue as well as digital viewing experience at an affordable price."

The TV520 reference design is built on the Nexperia Home media processor, which provides the IP blocks for MPEG de-multiplexing and decoding, video scaling, de-interlacing, noise reduction, all kinds of video featuring, video rendering, audio decoding, digital-to-analogue conversion and audio featuring. It also contains an HDMI and SD/HD analogue component input. The reference design is also scalable to higher-end TV solutions by simply adding a variety of NXP's companion processors.

The reference designs will be available in Europe and the Asia Pacific in Q1 2007.




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