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Chip packaging delivers 30% reduction in thickness

Posted: 03 Aug 2006     Print Version  Bookmark and Share

Keywords:Freescale Semiconductor  redistributed chip packaging  XX  XX  XX 

In an industry obsessed with miniaturization, Freescale Semiconductor Inc. has high hopes for a packaging technology that could radically alter the way chipsets are deployed.

A proprietary technique called redistributed chip packaging (RCP) delivers about a 30 per cent reduction in packaged-die area and thickness, said executives at the Freescale Technology Forum last week

Using photolithography and copper-plating steps to create chip-to-chip interconnects, RCP eventually will replace traditional wire bond, ball grid array and flip-chip packages, said Freescale chief executive Michel Mayer. Full-scale manufacturing is expected in 2008, Mayer said. At that time, Freescale expects to produce 20 crore (200 million) to 30 crore (300 million) RCP chips using internal manufacturing lines for PowerQuicc, DSP, baseband processor and power amplifier products.

Freescale plans to license the technology to packaging companies and other semiconductor vendors, making it an in- dustrywide standard, Mayer said. "We believe that RCP will have the right cost structure to make it a big deal right out of the gate." It could be used with SiP and package-on-package technologies, plus modules with integrated cavities, he said.

Sumit Sadana, Freescale's chief strategy officer, called RCP "a true breakthrough—we end up with a package that is only a little bit bigger than the die itself, and you don't need to deal with wire bonding or [flip chip's] C4 bumps." The approach cuts costs "without compromising on performance," he said.

In multichip modules used during the past two or three decades, chips were mounted on expensive low-temperature-coefficient ceramic substrates. "With LTCC, we mounted the die on the substrate. With RCP, we place the die in a panel and build interconnect around it," said Karl Johnson, a director at Freescale's lab in Tempe, Ariz., where the technology was developed over the past three years under team leader Beth Keser.

"That introduces the simplicity and elegance of proven semiconductor process techniques. And it eliminates the cause of defects, which come from stresses between the solder balls in flip-chip packages when they are attached to different substrate materials."

At the forum's technology lab, Freescale engineer Tran Phu demonstrated a side-by-side comparison of working GSM/Edge cell phone chipsets—one in the traditional plastic BGA packaging and the other in RCP. Using RCP, the entire GSM module—combining power management, RF, baseband and power amplifier chips—measured 2.5-by-2.5cm, about a quarter of the size of today's commercial GSM/Edge modules. Phu said additional optimisation can reduce the RCP implementation by 20 per cent more.

Freescale also demonstrated long-term-evolution OFDM devices for 3G phones, with one chip in a traditional BGA package measuring 13mm2 and another in RCP measuring 9mm2.

Sadana, a former IBM design engineer who is also Freescale's acting chief technology officer, said that RCP gives Freescale a means of combining, for example, an optimised radio frequency die, built using a silicon germanium process, with a digital IC for baseband and applications processing. By using optimised process technologies and then combining dice in an RCP module, Sadana said, Freescale could offer higher handset performance than its rivals.

Dozens of configurations
The RCP approach begins by separating each die within an IC and placing the individual dice into a grid configuration in a panel the size of a 200mm wafer, said Johnson. Dozens of combinations of the four GSM/Edge chips, for example, could be arranged on the panel and attached with adhesives. Epoxy and moulding compound are applied to the die, connection patterns are lithographically defined, vias are etched through a dielectric to the chip's I/O pad contacts and copper interconnects are electroplated. Because all of the chips in a module are packaged together, the approach eliminates wire bonding, as well as solder reflow techniques and flip-chip C4 solder bumps.

These photolithography, etch and plating steps result in one or two interconnect levels on both the top and bottom layers of a die, connecting the dice on the top side and providing links to the system substrate on the bottom. The copper interconnects on the top side of the die provide chip-to-chip connections. On the bottom side, RCP techniques are used to define either land grid arrays or C5 balls to link the die to the substrate of a cell phone handset, for example.

While RCP packaging would require masks to define the connections between the dice, they would be at micron-level resolution—3 to 10μm, depending on the chip's function—at a cost of perhaps $10,000 per mask set, Johnson said. "These are cheap masks, not the high-resolution masks needed to make 90nm or 65nm chips," he said.

The method is compatible with the fragile ultralow-k dielectrics used to insulate chip-level interconnects, while the manufacturing method is lead-free and in compliance with the European Union's RoHS regulations. The method can be used with single chips or multichip modules. And because RCP reduces stress between packaged dice, it could be used to integrate silicon-based logic circuits with memories, passives, accelerometers, sensors and GaAs devices, Johnson said. Extremely thin packages can be realised without thinning the die.

Because the dice are not handled by pick-and-place equipment, RCP enables thin packages within which several dice are placed side-by-side or, in some cases, stacked vertically. "RCP gives us a 30 per cent reduction in size and thickness," Johnson said.

The technology is being moved from the Tempe lab to a pilot line that will be in operation next year. The next step is to create volume-manufacturing lines by late 2007 and in 2008 at Freescale fabs worldwide. Also, Freescale will enable its external packaging partners to use RCP.

- David Lammers and Loring Wirbel
EE Times




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