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EDA/IP  

Formal verification tool provides fine control over thoroughness

Posted: 27 Jul 2006     Print Version  Bookmark and Share

Keywords:Averant  formal verification tool  Solidify 4.0  formal tool  XX 

Privately held EDA vendor Averant Inc. released the next generation of its formal verification tool, Solidify 4.0, offering what the company claims is the industry's first formal tool to give designers fine control over the tool's thoroughness.

According to executives from Averant, Solidify's guided proof system enables designers to use the tool to conduct rapid "bug hunting" exercises early on in the design cycle, then more exhaustive proofs of assertions later in the design cycle.

"There are cases where you are generating tens of thousands of properties, and you really need to have them run over night on a single computer," said Averant President Ramin Hojati. "And there are also cases where someone really wants to know if one property is going to pass, and has to spend a lot of time with it. This tool gives designers great flexibility to decide how much time they want to spend."

According to Hojati, early in the design cycle during bug hunting, the user may need to process 100 properties in seconds on a single computer. Later, when the focus shifts to exhaustive proofs, the user may have days and several machines to process these properties, Hojati said. By trading off completeness and accuracy against CPU time, Solidify can provide early feedback, while achieving maximum use of available compute power, he said.

Solidify 4.0 also includes other enhancements, including support for the entire SystemVerilog Assertion (SVA) language. Also supported is the use of inline SVA, verification IP attached through the bind command, and the Open Verilog Library (OVL) implemented in SVA, according to Averant.

Solidify 4.0 also introduces the ability—claimed to be another industry first—to translate between several property languages including SVA, PSL, OVA, OVL and HPL, giving design teams freedom to choose the property language that best serves their needs, and enabling preservation and reuse of verification intellectual property (IP). Other enhancements to Solidify 4.0 include extended debugging capabilities and clock crossing checks, as well as support for PSL version 1.1, according to Averant. Solidify now handles any mix of Verilog descriptions in the same design, Averant said. The Solidify also supports Liberty's cell format, the company said.

"We feel that this release, with the abilities that it adds, especially the guided proof system, and removing the issue of languages, gives people more of a peace of mind," Hojati said. Solidify 4.0 will be available in August on Linux, Windows and Solaris platforms, Averant said. Hojati declined to reveal the price of the tool, but did say that Averant has "reconfigured the product a little bit," adding property code coverage, which he described as being directly analogous to code coverage in simulation and unique in the static verification world.

- Dylan McGrath
EE Times




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