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EDA tool suite maximizes yield, performance at 65nm and below

Posted: 20 Jul 2006     Print Version  Bookmark and Share

Keywords:Anova  Anova Suite  Fujitsu  EDA tool 

A team of design-tool engineers has formed Anova Solutions Inc. and created an EDA tool suite to analyse process and design variations to maximize yield and performance in 65nm and below designs. Working with Fujitsu Ltd, the company has developed the Anova Suite centred on a unified variation model generator promising to reduce design uncertainties and unnecessary margins to maximize high-end silicon potential.

The analysis suite assists in making of effective decisions in design capabilities when moving to a smaller process and in estimating if the move is going to be effective in improving a design's performance.

"From our team's experience in developing the industry-standard ECSM model, we believe ECSM or CCS, which targets timing nonlinerarities and signal integrity accuracy, is inadequate. The next generation of signoff needs to be variation aware," said Anova founder, CEO and president Jun Li. "The invisibilities in the smaller design processes make it almost impossible to know if your design will function at 65nm, even if you do reduce design size and improve performance. As a result, designers have to include enormous and unnecessary margins in a design, reducing functionality and increasing the amount of time it takes to produce a chip. Our analysis suite can effectively eliminate that uncertainty and decrease decision-making time by multiple orders of magnitude."

The Anova Suite's unified variation model captures the process and transistor device variation, describes the variation in timing and power libraries, and provides the variation constraints to the design, including correlations, possibilities and best/worst cases. Using the suite, the company said, designers can reduce the margin to maximize the potential of a leading edge process; reduce turn-around time by limiting corners in the lithography; insert flexibility in the variation signoff; and accelerate the product yield ramp by linking the variation with process-critical parameters.

Anova delivered the layout based variation analysis engine to Fujitsu in December 2005. The stochastic analysis process engine for model generation (patent pending) was delivered in April 2006.




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