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Transceivers designed for multipoint bus apps

Posted: 18 Jul 2006     Print Version  Bookmark and Share

Keywords:National  LVDS transceiver  DS91C176  DS91D176  DS91C180 

National Semiconductor Corp. has introduced four multipoint-low voltage differential signalling (M-LVDS) line drivers and receivers compliant to the EIA/TIA-899 M-LVDS standard.

The company said the DS91C176, DS91D176, DS91C180 and DS91D180 transceivers have superior drive capability and can support up to 32 loads at clock frequencies up to 100MHz and data rates up to 200Mbps. The M-LVDS transceivers were designed specifically for multipoint bus applications where a common bus connects multiple drivers and receivers. They promise balanced, controlled edge rates and feedback-enhanced outputs that maintain constant amplitude over a wide range of load conditions. This provides the highest noise margin in backplanes at frequencies up to 100MHz, National said.

The Advanced Telecom and Computing Architecture (ATCA) standard specifies M-LVDS as the interface for backplane synchronization clocks. These devices designed for clock distribution in ATCA platforms or other multipoint backplanes.

Along with increased drive, National said the M-LVDS transceivers have a typical controlled edge rate of 2ns that minimizes signal reflections and EMI, and improves tolerance of unterminated backplane stubs. The transceivers also have a large common-mode range for additional noise margin in heavily loaded and noisy backplane environments.

Available in 8-pin SOIC narrow packages, the DS91C176 and DS91D176 are M-LVDS differential, half-duplex transceivers that accept LVTTL/LVCMOS signals at the driver input and convert them to differential M-LVDS signal levels. They operate up to 100MHz for clocks and 200Mbps for data. The receiver inputs accept low-voltage differential signals (LVDS, B-LVDS, M-LVDS and LV-PECL) and convert them to 3V LVCMOS signals. The DS91C176 receiver contains an M-LVDS type 2 failsafe circuit with an internal 100mV offset that provides a LOW output for both short and open-input conditions.

Available in 14-pin SOIC narrow packages, the DS91D180 and DS91C180 contain a full-duplex M-LVDS line driver and receiver. They operate up to 100MHz for clocks and 200Mbps for data. The driver input accepts LVTTL/LVCMOS signals and convert them to differential M-LVDS signal levels. The receiver accepts low-voltage differential signals (LVDS, B-LVDS, M-LVDS, LV-PECL) and converts them to 3V LVCMOS signals. The DS91C180 receiver contains an M-LVDS type 2 failsafe circuit with an internal 100mV offset that provides a LOW output for both short and open input conditions.

Already available, the DS91C176, DS91D176, DS91C180 and DS91D180 are priced at Rs.84.79 ($1.85) each in 1,000-unit quantities.




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Related Datasheets
Part Number Description Category
DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair EDA - Embedded Systems Design
DS91D176 100 MHz Single Channel M-LVDS Transceivers EDA - Embedded Systems Design
DS91D180 100 MHz M-LVDS Line Driver/Receiver Pair EDA - Embedded Systems Design
DS91C176 100 MHz Single Channel M-LVDS Transceivers EDA - Embedded Systems Design

 
 
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