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CEVA expands DSP cores, platform family

Posted: 02 Jun 2006     Print Version  Bookmark and Share

Keywords:CEVA  CEVA-X1622  DSP core  CEVA-XS1102  system platform 

CEVA Inc. has introduced the CEVA-X1622 DSP core and the CEVA-XS1102 system platform, the latest additions to its CEVA-X family of DSP cores and platforms.

These latest DSP offerings are already available for broad licensing, and extend the CEVA-X architecture based product line targeted for the 3.5G/HSDPA handsets, WiMax/WiBro terminals and Smartphones.

The CEVA-X1622 is a high-performance, low-power, fully synthesizable DSP with enhanced memory architecture, including configurable memory size (64Kbytes or 128Kbytes) and configurable memory bank organisation in two or four blocks. CEVA said that the flexible memory architecture allows the customer to make an optimal cost/performance selection in line with market needs. In addition, this DSP core offers a reduced gate count compared to other CEVA-X family members. Using an area-optimised implementation and On-chip Emulation Module (OCEM) enhancements, said the press release, this new product achieves a significant area reduction compared to the CEVA-X1620, making it ideal for advanced baseband and other mobile applications.

The CEVA-XS1102 is a "complete" DSP system platform built around the CEVA-X1622 DSP core. It includes additional peripherals and system interfaces for efficient system design.

According to the company, the CEVA-XS1102 offers customers reduced development costs and time to market, coupled with the user flexibility and reduced area offered by the CEVA-X1622 DSP core.

In addition, the CEVA-X1622 offers backward code compatibility to the CEVA-X1620 DSP, enabling licensees of the CEVA-X1622 DSP to leverage the broad range of software and components already available for the CEVA-X architecture.

"These additions to the highly successful family of CEVA-X DSP cores and platforms deliver important enhancements that will enable critical differentiation in communications and consumer applications," said CEVA CEO Gideon Wertheizer. "The CEVA-X1622 strengthens our breadth of offerings in leading-edge DSP core technology with a solution that lowers cost and reduces die size."

The CEVA-X1622 DSP core features a 16-bit fixed-point dual-MAC very long instruction word (VLIW) architecture combined with a Single Instruction Multiple Data (SIMD) multimedia operations, up to eight instructions executed in parallel, variable instruction widths (16- or 32-bit) and 4Gbytes of byte-addressable memory space. CEVA added that the numerous multimedia instructions and mechanisms built into the CEVA-X architecture enable the processor to dramatically accelerate advanced video compression standards on a truly software programmable platform.




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