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Synopsys announces first Verification Library

Posted: 27 Mar 2006     Print Version  Bookmark and Share

Keywords:Synopsys Inc.  VCS Verification Library  verification intellectual property 

Synopsys Inc. has announced that its VCS Verification Library, containing DesignWare verification intellectual property (VIP), is first to support testbenches created using IEEE Std 1800-2005 SystemVerilog and the coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog, published by Springer Science + Business Media.

Verification engineers who use SystemVerilog for testbench development now have access to a proven portfolio of Synopsys VIP to decrease the cost of testbench development, speed the time to reach coverage goals, and reduce risk in order to meet project schedules, said the press release. Verification IP support for SystemVerilog provides engineers with crucial building blocks for the development of more effective testbenches to address the challenge of SoC verification. This support enables more than 600 companies that use DesignWare verification IP to adopt a coverage-based verification methodology based on SystemVerilog and the VMM for SystemVerilog.

As the standard interfaces on SoC designs continue to increase in number and complexity, verification engineers are faced with tremendous challenges. Synopsys is leading the effort to solve these challenges with verification IP that helps simplify the creation of VMM-compliant testbenches and provides protocol-specific coverage. When combined with native testbench in the VCS solution, DesignWare Verification IP delivers up to 5X improvement in verification performance.

"With a considerable increase in the verification challenge for SoCs, verification engineers are asking for proven and fully-featured verification IP to reduce testbench development time and radically improve their verification productivity," said Guri Stark, vice president of marketing, solutions group at Synopsys.

The VMM for SystemVerilog provides verification engineers with a robust, consistent methodology for developing testbenches that help engineers meet the challenges of verifying today's complex SoC designs. The book defines a reusable constrained-random environment based on a coverage-driven methodology to increase verification productivity and quality. The verification IP contained in the VCS Verification Library provides essential SoC verification building blocks for VMM-compliant environments, resulting in a significant improvement for verification productivity.

Current customers of DesignWare Verification IP can gain access to the new functionality at no additional charge by requesting the SystemVerilog version from Synopsys' website. DesignWare Verification IP is available in the DesignWare Library, in the VCS Verification Library and as individual suites.




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