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EE Times-India > EDA/IP

Actel designs IP core for nonvalatile FPGAs

Posted: 23 Mar 2006     Print Version  Bookmark and Share

Keywords:CorePWM  IP core  PWM  pulse-width modulation  FPGA 

Actel Corp. introduced CorePWM, a flexible pulse-width modulation (PWM) intellectual property (IP) building block for D/A conversion, designed for the company's nonvolatile FPGAs. When implemented in an Actel Fusion programmable system chip (PSC), CorePWM is said to enable the design of a single-chip, closed-loop control system. According to Actel, the product suits embedded mixed-signal applications in the industrial, medical, military/aerospace, communications, consumer and automotive markets.

The IP core is said to use only 11 per cent of the logic of a 30,000-gate ProASIC3 or four per cent of a 90,000-gate Fusion device. It has a register-based interface that can be used with or without a microcontroller. The CorePWM has up to eight PWM output channels with 8bit PWM resolution and an 8bit prescaler. The core clock speed is 98MHz on an Actel Fusion device. The core can be used in embedded applications, including heating and cooling, motor control, motion control, voltage output adjustment and sound generation. Other Actel FPGA families supporting the core include ProASIC3, ProASIC Plus, Axcelerator and RTAX-S.

The CorePWM is available now and is priced at Rs.1,32,750 ($3,000) for a single-use netlist. A free evaluation version of the core is available for download from the company's website.

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