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LVDS buffer features on-chip termination

Posted: 20 Mar 2006     Print Version  Bookmark and Share

Keywords:DS90LV804  LVDS buffer  National Semiconductor 

National Semiconductor Corp. has introduced a very small, low-jitter signal integrity buffer to its portfolio of LVDS products.

National's DS90LV804, a four-channel LVDS buffer, operates from zero to 800Mbps. The device features 15kV of ESD protection for the isolation of FPGAs, ASICs and other onboard components. It is designed for delivering LVDS signals across cables and backplanes found in electronic systems, including telecom, industrial, medical, automotive and office imaging applications.

The DS90LV804 drives up to four LVDS clock and/or data channels over common backplanes or simple cable configurations. According to National, the wide differential input range easily interfaces to LVDS, low-voltage positive emitter-coupled logic or current-mode logic input levels. The output levels are fully LVDS-compliant.

The product's quad configuration has matched output drivers for a typical minimal channel-to-channel skew of 50ps. On-board terminations are said to help reduce jitter by terminating the signal path at the transmit output and at the receiver input. Total typical jitter is a 30ps.

When high-speed signals pass through cables or PC boards, the signal integrity is highly dependent on the data rate, cable type, length, termination scheme and environmental noise. The DS90LV804 has both internal input and output, or source termination resistors that aim to maximize signal integrity.

The DS90LV804 is available in a 32-pin LLP package that measures 5-by-5-by-0.80mm. Pb-free package options are also available.




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Related Datasheets
Part Number Description Category
DS90LV804 Four-Channel 800 Mbps LVDS Repeater EDA - Embedded Systems Design

 
 
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