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Bluespec, Indian institutes partner on design methodology course

Posted: 20 Jan 2006     Print Version  Bookmark and Share

Keywords:Bluespec  MIT  Indian university  course  IC design 

Smaller silicon geometries have delivered the possibility of developing design featuring millions of gates to hardware designers. This has, however, been accompanied by a significant increase in design complexity and verification requirements and has stretched the capability of design engineers to keep in step with the startling pace of developments.

It is specifically this capability issue that Bluespec Inc., a US-based developer of high-level SystemVerilog-based ESL toolset, has sought to address in its association with Indian engineering institutes. The company is tying up with MS Ramaiah Institute, BITS, the IITs, and the IISc. Bluespec's core input to the institutes is its course on methodology for design of large, complex ICs, which is part of Massachusetts Institute of Technology's web-based publishing initiative OpenCourseWare (MIT OCW). Bluespec will also focus on faculty training, and have a separate licensing policy for universities, with unlimited copies of licenses.

MIT OCW offers free, open access to educational materials from 1,259 MIT courses for educators and students around the world for self-study or supplementary use. Recently, MIT OCW added course material that teaches a methodology for the design of multi-million gate ICs. The backbone of the course is the methodology of Bluespec's electronic system level (ESL) synthesis software. The "Course 6.884 - Complex digital systems" was developed by MIT's Professor Arvind, one of Bluespec's founders and Directors, and Associate Professor Krste Asanovic.

"It's time to set a new bar in what we can expect students to have designed while in college," said Shiv Tasker, CEO, Bluespec. "The days of designing a filter as your master's thesis are long gone. We should expect students to implement a million-gate design in a semester."

Bluespec's EDA software toolset incorporates Term Rewriting Systems (TRS)-based synthesis, a technology developed by MIT Professor Arvind and his students, to enable hardware designers to generate control logic on a correct-by-compiler construction basis. Hardware designers can raise the level of abstraction of ASIC and FPGA designs, while retaining the ability to automatically synthesize RTL code, without compromising speed, power or area. This methodology reduces development costs for complex, customisable designs, allowing semiconductor manufacturers to support smaller markets with more targeted solutions.

Materials posted online related to Bluespec are course lecture notes and laboratory material that include descriptions and information on technology and scaling; area, delay, and power dissipation of gates and interconnect; VLSI implementation styles emphasizing cell-based ICs and FPGAs; hardware description languages (HDLs) including Verilog and Bluespec; clocking, power distribution, packaging, I/O and fabrication testing.

The course is available at http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-884Spring-2005/CourseHome/index.htm.




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