Global Sources
EE Times-India
Stay in touch with EE Times India
 
EE Times-India > T&M
 
 
T&M  

National announces wafer-level package technology

Posted: 13 Jan 2006     Print Version  Bookmark and Share

Keywords:National Semiconductor  micro SMDxt  micro Surface Mount Device extended technology  chip package 

National Semiconductor Corp. announced the micro SMDxt (micro Surface Mount Device extended technology) chip package, its newest generation of wafer-level package technologies.

This package, which builds on the company's micro SMD, uses a "unique" structure that enables high-reliability products with bump counts of 42 to 100 bumps at a 0.5mm pitch without any underfill. Higher bump-count packages enable designers to create more complex products with advanced features and pack them into a smaller space.

"National leads the industry in package miniaturisation for applications such as cell phones, notebook computers and other portable devices," said Sadanand Patil, VP of National's Package Technology Group. "The micro SMDxt package offers the industry's smallest footprint and improved performance while using standard surface mount assembly and rework processes."

The superior electrical noise performance of the micro SMDxt package (compared to standard wire-bonded devices) makes it well-suited for high-performance mobile applications. Thermal performance of the package is comparable to other thermally enhanced packages such as QFN or LLP packages with similar pin count. Reliability standards such as thermal cycling, thermal shock and drop test, and flex test can be met without the use of an underfill, added National.




Comment on "National announces wafer-level packa..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top