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Leakage shrinks DFM yield at 90nm, 65nm

Posted: 01 Dec 2005     Print Version  Bookmark and Share

Keywords:90nm  design-for-manufacturing  DFM  International Business Strategies  Fabless Semiconductor Association Expo 

Reducing leakage current is a well-known design challenge at 90nm and below. But leakage is also a design-for-manufacturing (DFM) problem that has become a source of design-related yield loss, some industry observers say.

Handel Jones, CEO of International Business Strategies Inc., came to the Fabless Semiconductor Association Expo with a harsh warning. In a panel presentation, he said that DFM factors have slowed the ramp-up to 90nm wafer volumes and threaten to delay 65nm even further. And, Jones said, leakage is the major reason for DFM yield loss.

While some industry insiders see leakage as a potential culprit in yield loss, most wouldn't say it's the primary factor. Others see leakage as a design issue, not a yield problem. No one disagrees that the problem is severe at 90nm and worse at 65nm.

"Assuming you have defect density under control, as major companies do, leakage is the largest contributor to yield losses," Jones said. "The industry is not really 'fessing up to the problem. It was starting to be acknowledged, but I think it's being swept under the rug again at 65nm."

Because of DFM factors, Jones said, the ramp-up to 90nm-production wafers has taken more than two years and the ramp-up to 65nm may take nearly three, compared with 1.5 years for 130nm. The industry traditionally thinks in terms of random-defect-related yield, noted Marc Levitt, DFM platform vice president at Cadence Design Systems Inc. But if you start to consider parametric yieldwhat Jones would call design-related yield lossthen leakage and power issues become very important, he said.

"You might do a functional test and find that 70 per cent of your dice are good," Levitt said. "Then you do a leakage test and find you're above a certain number of milliamps and that 70 per cent suddenly drops to 35 per cent. So you could have a 35 per cent yield loss because of leakage."

Leakage can also cause hot spots in a design and perhaps even thermal runaway. In extreme cases, said Nitin Deo, vice president of marketing at DFM startup Ponte Solutions Inc., it can lead to catastrophic failures such as dislocation-induced leakage between the source and drain of a transistor. "Leakage is one of the major sources of parametric failure," Deo said. "It is underestimated today. Designers do not have an understanding of leakage as a source of yield lossthey see it only as a performance or power factor."

Synopsys Inc. makes a distinction between random and systematic yield, with the latter referring to things that are systematically happening. "Leakage has become a key driver of the systematic segment of the yield-loss mechanism," said Anantha Sethuraman, vice president of DFM for the silicon engineering group.

Foundries have mixed views. Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) views leakage as a design rather than a yield issue, a spokesman said. But TSMC has made leakage reduction a primary goal of its recently introduced 65nm reference flow. United Microelectronics Corp. (UMC) thinks differently. "Yield loss caused by leakage is contributed by higher power consumption, which may impact design performance through a rise in temperature," said Suzanna Chang, senior director of marketing at UMC.

Gary Smith, chief EDA analyst at Gartner Dataquest, doesn't think leakage will cause yield loss unless it's detected through Iddq testing. But leakage can show up in power or timing failures caused by regional heating, he noted.

"Power-limited yield loss is a reality," said Andrew Khang, founder and chairman of startup Blaze DFM Inc. "Typically, such bad parts are detected using Iddq testing." Khang added that systematic, parametric yield loss will start to eclipse random defects at future process nodes.

An insidious problem
With the reduction in voltage thresholds and with thinner gate oxides, leakage problems are beginning to increase exponentially. Leakage may be responsible for 50 per cent of a chip's power consumption at 90nm and perhaps as much as 80 per cent at 65nm.

According to Jones' studies, both subthreshold and gate-oxide leakage are growing faster than dynamic power, although high-k materials may slow gate-oxide leakage somewhat. Leakage is also extremely susceptible to process, temperature and voltage variations. It is strongly interdependent with temperature, and just as leakage can cause hot spots, thermal gradients can cause huge increases in leakage. Critical-dimension variations can also wreak havoc with leakage.

Leakage variation can be as much as fivefold, said Robert Hoogenstryd, director of marketing implementation at Synopsys. "If your chip is consuming five times as much leakage current as expected, the chip will run hotter and may eventually melt, or not perform because of temperature inversion," he said

Fortunately, leakage can be reduced by swapping in high-voltage-threshold cells where performance is not critical. For this reason, many 90 and 65nm processes provide low- and high-Vt libraries. Designers can also set up voltage islands and power-down sections of the chip that aren't in use.

TSMC's 65nm reference flow offers power-gating technology based on multithreshold CMOS, letting users insert high-Vt footers to shut down circuits that are not operating. Intel Corp. claims its recently introduced P1265 process reduces transistor leakage 1,000 times over its high-performance 65nm process. The trade-off is that transistor performance is lower by a factor of two. IBM and Texas Instruments have also introduced 65nm processes that claim lower leakage.

Both resolution enhancement technology and lithography simulation can also help, said Blaze DFM's Khang. But more needs to be done. "We will see future tools that reduce leakage and improve power-limited yield while being aware of both design and process constraints," he said.

- Richard Goering
EE Times




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