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ESL methodologies can improve productivity

Posted: 01 Aug 2005     Print Version  Bookmark and Share

Keywords:esl  electronic system level 

There is a strong feeling within the design community that electronic system level (ESL) methodologies can improve productivity, according to the results of a survey conducted by ESL Now, a loose organization of more than 20 companies focused on encouraging ESL adoption.

Of the 141 respondents to the online survey, which was conducted in late May and early June, more than 98 percent answered that they either agree or strongly agree that ESL methodologies can strongly improve productivity.

AK Kalekos, vice president of marketing and business development at ESL tool provider CoWare (San Jose, Calif.), said the results were not a surprise to the members of ESL Now.

"Clearly, this was the way we expected the results would go," Kalekos said. "The System C and System Verilog wars seem to have been settled and System C is the winner. It is only natural that System C is growing at the rate that it is."

Among the other results of the survey, when asked the type of designs they are currently working on, 31.7 percent of respondents said system-on-chip (SoC) designs, followed by field-programmable gate arrays (FPGAs) at 27.7 percent and ASICs at 24.7 percent.

The complete results of the survey are now available on the ESL Now Web site.

ESL Now members include EDA giants Cadence Design Automation Inc., Mentor Graphics Corp. and Synopsys Inc., among others.

- Dylan McGrath

EE Times





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