Global Sources
EE Times-India
Stay in touch with EE Times India
EE Times-India > Memory/Storage

How to interface DDR-II SRAMs with Stratix II devices

Posted: 08 Sep 2005     Print Version  Bookmark and Share


The DDR-II SRAM device generates echo clocks CQ and CQn, which are edge-aligned with the leading edge of the read data. The CQ and CQn signals are then phase-shifted inside the Stratix II device and used to capture the read data. The CQ and CQn signal board trace length between the DDR-II SRAM device and the controller should be equal to the data I/O (DQ) board trace length to minimize the skew between the two signals.

For Stratix II interfaces to DDR-II SRAMs, connect the CQ and CQn pins to the FPGA DQS and DQSn pins, respectively. Both phase-shifted CQ and CQn signals are used to capture the read data. The CQ pin is connected to the input latch and the active-high input register, while the CQn pin is connected to the active-low input register.

For best data alignment, invert the CQ and CQn signals before they arrive at the DQ IOE registers. This option can be selected in the altdq megafunction.

Use regular I/O pins in Stratix II I/O banks 3, 4, 7, or 8 via the double data rate (DDR) registers to generate the K and Kn clocks. To meet the DDR-II tKHKH (skew between K and Kn) requirement, use adjacent pins for the complementary signals and surround the pin-pair with programmable VDD and ground pins for better noise immunity.

Data signals

DDR-II SRAM devices use bidirectional data buses, for writes and reads (DQ). Connect DQ pins on the SRAM to the DQ pins on the Stratix II FPGA. Any of the FPGA user I/O pins in I/O banks 3, 4, 7 or 8 can be used to connect to the DQ ports.

Control signals

DDR-II SRAM devices use the R/W signal to indicate write and read operations, while the Synchronous Load (LD) is used to indicate the start of the operation. The byte write select signal (BWSn) is a third control signal that tells the DDR-II SRAM device which byte to write into or read from the DDR-II SRAM device. Any of the FPGA user I/O pins in I/O banks 3, 4, 7 or 8 can be used to generate control signals.

Address signals

DDR-II SRAM devices use one address bus (A) for both read and write addresses. Any of the FPGA user I/O pins in I/O banks 3, 4, 7 or 8 can be used to generate address signals.

DDR-II SRAM interface architecture

For the write implementation, a write PLL is used to generate the write data (D) and center aligned system clocks (K and Kn) using the dedicated DDR I/O circuits. This implementation results in matched propagation delays for clock and data signals from the FPGA to the DDR-II SRAM, minimizing skew. For the read implementation, the enhanced DLL and delay shift circuitry are used to center align the echo clocks (CQ and CQn) with read data (Q).

Datapath architecture in Stratix II

The DDR-II implementation in Stratix II uses two PLLs: - A write PLL generates K/Kn system clocks and clock out address, command, and data. - A read DLL-based phase shift circuitry registers read data from the memory using echo clocks CQ/CQn.

Figure 4

Figure 4 depicts the memory interface datapath architecture. Specifically, it indicates how to connect the clocks, data, address, and control pins in Stratix II devices when interfacing with DDR-II SRAM devices. The write PLL generates two clock outputs, WRITE_CLK and WRITE_CLK_90 that have a 90 phase offset. The WRITE_CLK output is used to clock out the address, command, and data signals to the DDR-II SRAM, while the WRITE_CLK_90 output is used to generate the K/Kn memory input clocks. This architecture centrally aligns the K and Kn write clock edges to the output data (D) and address (A) signals. Write data outputs to the memory and the clocks use the double-data rate registers or DDIO circuitry in the IO cell, significantly minimizing the skew between clock and data channels.

The read DQS phase shift circuitry generates a centrally aligned version of CQ and CQn echo clocks for read data capture. The captured data can then be resynchronized to the system clock.

Timing analysis

Since data is transferred between the FPGA memory controller and the DDR-II SRAM device at high speeds, it is imperative to avoid set-up or hold violations for the DDR-II SRAM and the FPGA. This section illustrates the timing analysis that must be performed when designing a high-speed DDR-II SRAM interface.

Write cycle timing

It is essential to meet the DDR-II SRAM device set-up and hold requirements for correct write cycle timing. For example, the data set-up and hold specifications for the Cypress burst-of-2 267MHz devices are 0.35ns each.

The FPGA controller drives both the DDR-II SRAM clock and data signals. The board delays for the clock and data (DQ) lines may not be equal and hence, to offset any mismatch in trace lengths, a factor of 50ps is considered in the clock-to-output delay calculations.

Because K and Kn are generated from the WRITE_CLK_90 signal, while data and address are generated from the WRITE_CLOCK signal, there is a timing margin of approximately one-half of the bit period (the length of time between each data bit) each way to meet the DDR-II SRAM device set-up and hold times. The bit period, by definition, is approximately one-half of the cycle time for double data rate signaling.

Figure 5

In addition to set-up and hold times, an additional concern is the clock-to-clock skew between K and Kn (tKHKH). The 267-MHz DDR-II SRAM specification calls for a minimum 1.8ns delay between the rising edges of the K and Kn signals. Because Stratix II device clock-to-out times can vary with pin position, K and Kn need to be placed on adjacent pins and their tCO times need to be verified to meet this requirement. For better noise immunity, it is recommended to surround the pin pair with programmable VDD and ground pins.

In the following exercise, we analyze the timing for a write operation from a Stratix II EP2S60 device to a Cypress CY7C1518AV18-267 burst-of-2 267MHz DDR-II SRAM device.

Let us start the timing analysis by studying the input clocks K and Kn. These clocks are generated by the WRITE_CLK_90 output of the PLL inside the FPGA. The data, address and command outputs are clocked out by a different output of the same PLL. Since two outputs of a PLL feeding global clock networks have an inherent skew, the K and Kn clocks could be offset from the data outputs by this amount. For the Stratix Enhanced PLLs, skew between two PLL outputs using different counters is 150 ps. This specification is listed in the DC and Switching Characteristics chapter in the Stratix II Device Handbook (Volume 1 Chapter 4). Figure 6 illustrates this and other uncertainties on the clock and data signals.

Figure 6

This results in a minimum phase offset between these two clocks: TSHIFT_MIN = (0.25 * clock period) - clock skew = 0.25 * 3750 - 150 = 787.5ps

Similarly, the maximum phase offset between the two PLL output clocks: TSHIFT_MAX = (0.25 * clock period) + clock skew = 0.25 * 3750 + 150 = 1087.5ps

In additionto this clock skew uncertainty, PLL outputs can have duty cycle distortion (DCD) up to 5 percent of the clock period. This results in an additional clock uncertainty of 187.5ps (5 percent of 267MHz clock). Another source of uncertainty on the clock is PLL jitter. However, since PLL jitter affects both the clock and data outputs to the memory uniformly, it does not affect the set-up/hold relationship on the DDR-II SRAM.

In Figure 6, for example, if the ideal clock edge of WRITE_CLK_90 is expected at time t = 3,750ps. After accounting for PLL output clock skew and duty cycle distortion, the clock edge can occur anytime between t = 3,412.5ps and t = 4087.5ps.

Next, we compute the uncertainties on the data (D) signals. Channel-to-channel skew among all data pins is equal to the worst-case skew between the DDR outputs within the I/O bank(s). When using a single column I/O bank in the EP2S60 devices, the worst-case skew is tIOSKEW = 160ps. Additionally, board trace length variations could add to this channel-to-channel skew. While this implementation calls for perfectly matched trace lengths, the timing analysis allows for 50ps of board skew. These skew parameters affect the data valid window on the DDR-II memory and reduce it by 420ps.

previous page

next page

Comment on "How to interface DDR-II SRAMs with S..."
*  You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.


Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

Back to Top