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SiP: a window of opportunity for passives

Posted: 16 Sep 2005     Print Version  Bookmark and Share

Keywords:soc  sip  design engineer  system-on-chip  system-in-package 

In the great debate of system-on-chip (SoC) vs. system-in-package (SiP), design engineers usually get tangled in the delicate technical intricacies while missing an important point—the implications on the passive component industry.

The great SoC push has so far continued the integration of passives in ICs for smaller, lighter and cheaper devices in communications and consumer segments. This system-level integration had a huge impact on the discrete and passive component industry.

Subsequently, significant parts of passive components, such as connectors and antennas, ended up on both discrete transistor devices and ICs. But as they say, "no tree grows to sky." SoC scaling is not without physical limitations, and this has eventually helped the concept of SiP come to the fore.

One of the prime beneficiaries of a successful SiP foray would be the passive component industry, which has been barraged by the integration enterprise that came with the SoC drive. Although integration is still the main theme in the SiP bandwagon, it comes with some breathing space.

It'd be worthwhile to note at this point that SiPs still pose design challenges in terms of passive integration, especially in the RF domain. In SiP solutions, passive components are integrated into IC-sized packages along with active components.

The greater assimilation of passive components onto SiP platforms would rely on factors such as cost-per-unit area of silicon and performance considerations like minimum lead lengths to reduce parasitic inductance.

Then there are assembly factors such as reducing the number of bonding pads between the active die and passive integration substrate. Process technology would also be a critical issue from a yield standpoint.

All these imply that passive component makers may have to raise the R&D bar in terms of providing new value proposition, which will include high-density capacitors, low-ohmic value interconnects and high Q-factor inductors.

It's about time for passive component makers in Asia to objectively evaluate the merits of SiP technology and find out where they stand in this window of opportunity. This may also help them rise above the overriding driver—cost—and take the battle to new frontiers like product development and the emerging high-tech areas of componentry.

Understanding the current and future needs of their customers could well be on top of the agenda of passive component makers and, for that matter, they must work closely with OEMs and ESM providers at the design stage. Here, innovation and a clear understanding of new technology drivers would be crucial.

So SiP nomenclature may well find some leading slots in the diaries of some passive component makers.

- Majeed Ahmad

Electronic Engineering Times-Asia




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