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Packaging conference to explore 3D, SIP

Posted: 21 Oct 2005     Print Version  Bookmark and Share

Keywords:national semiconductor  sip  wafer-level packaging  3d chip packaging 

Building on the first International Wafer-Level Packaging Congress (IWLPC) event, the second IWLPC conference will explore three-dimensional (3D) chip-packaging and other technologies.

The second IWLPC event is scheduled for November 3-4, at the Doubletree Hotel in San Jose, Calif. It is co-sponsored by Chip Scale Review Magazine and the SMTA.

Ken Gilleo of ET-Trends LLC and Luu Nguyen of National Semiconductor Corp. have been appointed co-chairs for the program, which will include multiple-track sessions as well as panel presentations and exhibits by leading industry providers of equipment, materials, and services.

The event will explore cutting edge semiconductor packaging with presentations on topics that include chip scale packaging, 3D packaging, system-in-package, system-on-chip, system-on-package, and wafer-level packaging.





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