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Same-die tactic eases DDR transition

Posted: 15 Apr 2001     Print Version  Bookmark and Share

Keywords:dram  ddr  jedec  memory density  sdr 

In the DRAM industry, the year 2000 can be now viewed as the real coming-out of double-data-rate (DDR) DRAM. The DDR device specification was standardized at the Joint Electronic Device Engineering Council (Jedec), and new DDR products and support emerged. Among them were the common Gerber design for the DDR memory module, the introduction of a DDR support chipset, and finally the launch of a DDR-based PC in the fourth quarter. Many more DDR-based PCs are expected to hit the market this year, and DDR-based server launches are planned throughout the industry during 2001.

Most of the major DRAM vendors have already completed the product development of DDR with both 128Mb and 256Mb densities that meet the sweet-spot density for PCs and servers.

Considering the radical rise expected in both CPU and front-side bus (FSB) speeds during the next couple of years, it was obvious that the inherent memory bandwidth of each DRAM device needed to double. The DDR SDRAM architecture is the natural successor to the current single-data-rate (SDR) SDRAM main memory solution for computing systems. DDR allows system developers to enjoy the performance headroom of the new high-power CPUs. The industry consensus is clear: DDR's time has come.

Now several issues come to the forefront. What design issues must engineers consider, and what can DRAM suppliers do to make this main memory transition happen smoothly and seamlessly? It will definitely take some time to migrate from the previous SDR designs to the higher-performance DDR architecture. On the up side, because the transition is evolutionary, the system design issues are fairly straightforward, with minimal effort and time lost to re-architect the system, as well as minimal impact on the overall system cost.

System design engineers need to consider a couple of new features for their DDR systems—the stub-series terminated logic (SSTL) interface bus and the source-synchronous data capturing—as well as optimizing the motherboard design and stack-up for DDR. DRAM suppliers have collaborated with system developers on these issues in recent years, producing reference design guides or the Gerber design.

During this transition period the important and perhaps the biggest issue for DRAM suppliers is how to achieve a flexible production mix of either SDR or DDR SDRAM. DRAM suppliers must support fluctuating requests from system developers. Currently, the design cycles at many system OEMs are becoming much shorter—only three months for PCs and even less for some server systems. Under these circumstances, OEM system development projects are reviewed monthly, and so is the decision of which memory technology to be used. To keep pace with the changing design environment, DRAM suppliers must be able to supply either SDR or DDR on a short-term basis, even though the midterm trend toward DDR for mainstream applications is clear.

Die sharing saves cost

One solution that promotes a flexible product mix supporting both memories lies in the design and production of the DRAM die. It is now possible, practical and even cost-effective to design a DRAM device that is compatible with both the SDR and DDR SDRAM architectures. The SDR and DDR functions can be implemented either by wire-bonding in the assembly or by the metal-layer mask at the end of the wafer-fabrication process. This allows the DRAM suppliers to change the production mix of SDR vs. DDR in a short time, compared with the turnaround time when the architecture selection is initiated at the very beginning of the wafer-production process.

For DRAM suppliers, the production of same-die SDR or DDR will dramatically lessen the difficulties and the risks of controlling the inventory in the wafer-production lines, and it also provides a big incentive for them to boost production volumes. Design engineers can decide which device to use later in the system design cycle, without worrying if the right product will be available. Of course, the designer must eventually choose one or the other.

DRAM suppliers do face a couple of challenges in truly enabling an SDR/DDR-compatible die. However, the solutions for that challenge are reasonably within reach for most DRAM vendors. This same-die production process is a feasible and realistic approach, which Elpida has already taken.

From the die design perspective, there are major differences between SDR and DDR to realize the doubling of the frequency and rate of data-in and data-out of the device. Based on a standard SDR design, the DDR die employs several additional functions. It offers doubling of the data-bus width (number of data-bus lines) in the memory array, an embedded DLL-clock synchronizing circuit and an SSTL-2 interface input buffer with high-speed and small-swing input (SDRAM has a low-voltage transistor-transistor logic, or LVTTL, interface input buffer). Those functions are key for the DRAM die to enable DDR performance and specifications. However, these functions raise other design points in order for the same die to cover SDR functionality.

Area to spare

First, consider the case of the data-bus lines in the memory array. Doubling the data-bus width in a memory array can be easily done in the current 0.18µm or 0.15µm process. The effect on the die area of the data bus in the memory array is only about 2 percent. That is not a significant number.

Next up, there are some layout considerations for the delay-lock loop (DLL) circuit, such as the placement and routing of the signal and power lines. These are required to ensure the stable and accurate timing control for the whole circuit. However, the cross area in the memory arrays can be used for the DLL circuit while meeting the considerations above, and the effect on the die area can be also minimized within a few percent.

Finally, in the case of the input buffer, there are a couple of solutions for crafting a compatible design for both the SSTL interface and the LVTTL interface. In terms of speed, sensitivity and power, the details may differ depending on the circuit technology of each DRAM supplier.

In a conventional input buffer, a differential amplifier is used for the SSTL interface and a CMOS-gate amplifier is used for LVTTL interface. The differential amplifier can realize enough speed and sensitivity for the high-frequency input at the small swing level of SSTL. This circuit is still compatible in terms of speed and sensitivity for relatively lower-frequency input at the full swing level of LVTTL. However, this also causes a penetrating current at each buffer and an increase in power consumption.

The input-buffer circuitry that Elpida designed for the second-generation DDR die is compatible with SDR. This input buffer is based on the combination of two complementary differential amplifiers with added circuitry to reduce power for both the SSTL and the LVTTL interfaces.

Jun Kitano

Elpida Memory Inc.





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