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Scripts bind EDA tools

Posted: 01 Jun 2001     Print Version  Bookmark and Share

Keywords:isqed  swig  verilog  design automation 

Tucked away in the proceedings of the International Symposium on the Quality of Electronic Design (ISQED) is an interesting paper that could help EDA users struggling with interoperability. The paper promotes an easy, low-cost way to link EDA tools' application programming interfaces with popular scripting languages such as Perl and Tcl.

Authored by researchers from the University of California at Berkeley and Intel, the paper was part of a track on EDA tool quality. It shows how to link EDA tools with scripting languages using an "interface wrapper generator."

The approach outlined in the paper can provide a full scripting or programming capability for a tool that might otherwise not have it. But more significantly, the authors claimed the approach can make tools from different EDA vendors interoperable at the API level.

The scripting language glues the tools together so that all tools are dynamically loadable. You just choose the capabilities you need for a given task and go. Tool vendors can develop and upgrade their applications independently. It is generally not easy to integrate EDA tool APIs with scripting languages, the authors noted, but the task is made much easier by using the Simplified Wrapper and Interface Generator (Swig) to automatically generate interfaces.

Swig is probably more familiar to software engineers than chip designers. This public-domain software development tool connects programs written in C/C++ with a variety of high-level programming languages. It is the product of all-volunteer users, which can be found at www.swig.org.

The ISQED paper shows how to use Swig to link Perl and Tcl to EDA tool APIs. Most but not all of the necessary interface code can be generated by Swig, so the paper explains the extra coding that's needed. The paper's authors have a Web site at www-cad.eecs.berkeley .edu/~pinhong/scriptEDA/. In addition to the paper, this site has free Perl and Tcl interfaces for public-domain EDA programs and formats, including the Verilog PLI, the Cadence LEF and DEF formats, and the Synopsys ".lib" format.

Most of the papers in the ISQED proceedings are academically oriented, but I have to say I am very impressed by the quality of papers in this IEEE conference, which is just in its second year. There is a wealth of information on topics like verification, interconnect modeling, power-aware design, defect analysis and manufacturability.

Richard Goering

EE Times





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