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3 Volt Intel StrataFlash Memory to Intel IXP12x0 Network Processor Design Guide

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3 Volt Intel StrataFlash.

Memory

to Intel.

IXP12x0 Network

Processor Design Guide

Application Note 765

August 2002

Document Number: 251392-001

2

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL. PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel's website at http://www.intel.com.

Copyright ) Intel Corporation, 2002.

*Other names and brands may be claimed as the property of others.

3

AP-765

Contents

1.0 Introduction ..................................................................................................................5

2.0 3 Volt Intel StrataFlash.

Memory ........................................................................5

3.0 Intel.

IXP12x0 Network Processor Family.......................................................5

4.0 Hardware Interfaces..................................................................................................5

4.1 Flash Memory Interface.........................................................................................6

4.2 Microprocessor SRAM Unit Interface....................................................................7

4.3 Interface Considerations .......................................................................................8

4.4 Hardware Connections..........................................................................................8

5.0 Register Settings......................................................................................................10

5.1 SRAM_CSR Register (CSRs) .............................................................................10

5.2 SRAM_SLOW_CONFIG Register .......................................................................12

5.3 SRAM_BOOT_CONFIG Register .......................................................................13

6.0 Bus Operations and Timings...............................................................................14

6.1 Asynchronous Single Reads ...............................................................................15

6.2 Asynchronous Writes ..........................................................................................16

7.0 Summary......................................................................................................................16

Appendix A Additional Information ........................................................................................17

4

AP-765

Revision History

Date of

Revision

Version Description

07/26/02 -001 Initial Release

08/16/02 1.0 Revision based on review/inspection.

AP-765

5

1.0 Introduction

This application note provides hardware design information for system designers when interfacing

the 3 Volt Intel StrataFlash.

Memory to the Intel.

IXP12x0 Network Processor Family, which

includes the Intel.

IXP1200 device, the Intel.

IXP1240 device, and the Intel.

IXP1250 device.

This document discusses general concepts, hardware connections, and interface considerations

involved when interfacing the integrated features and control signals of the 3 Volt Intel

StrataFlash.

Memory (For additional information, refer to the 3 Volt Intel StrataFlash.

Memory

Datasheet).

This document is based on information available at the time of its publication (see Appendix A).

Any subsequent changes in device specifications may not be reflected in this document. Refer to

the appropriate documents or your local Intel sales office for the most current information.

2.0 3 Volt Intel StrataFlash.

Memory

The 3 Volt Intel StrataFlash.

Memory combines high performance page-mode and asynchronous

reads with reliable and proven two-bit-per-cell technology. Other benefits include more density in

less space, high-speed interface, support for code and data storage within the same device, and

Common Flash Interface (CFI) for easy migration to future devices. The 3 Volt Intel StrataFlash.

Memory (J3) is a NOR-based flash component on .25 5m lithography and is the second-generation

component in this product family.

3.0 Intel.

IXP12x0 Network Processor Family

The Intel.

IXP12x0 Network Processor Family is designed to meet the wide requirements placed

on networking equipment; from cost-effective entry-level products to high performance solutions.

These network devices cover a broad spectrum from multi-service switches and networking

appliances to broadband access platforms.

The IXP12x0 Network Processor is an integration of a range of high-speed processor cores with

programmable multithreaded Microengines and expanded instructions stores. Enhanced

functionality enables developers with the flexibility to meet a variety of requirements including

faster line speeds, multi-protocol support, data handling reliability, and lower costs.

4.0 Hardware Interfaces

This section describes the hardware interface signals of the 32Mbit 3 Volt Intel StrataFlash.

Memory and the IXP12x0 Network Processor. This document assumes that all other device signals

are connected in such a way as to ensure proper device operation.

AP-765

6

4.1 Flash Memory Interface

The hardware interface of the 32Mbit 3 Volt Intel StrataFlash.

Memory uses the following signals.

A0 Byte Address (input): Byte address bit when in x8 mode; disabled in x16 mode

(BYTE# = HIGH). Not used in this example design. The IXP12x0 does not support

x8 mode accesses.

A[23:1] Address (input): Program and read address inputs. Addresses are internally latched

during a program cycle.

D[7:0] Low-Byte Data Bus (I/O): Inputs data during buffer writes and programming.

Inputs commands during Command User Interface (CUI) writes. Outputs array,

query, or status data in the appropriate read mode. High-Z when the device is

deselected (CE#=high) or the outputs are disabled (OE#=high).

D[15:8] High-Byte Data Bus (I/O): Inputs data during x16 buffer writes and Programming

operations. Outputs array, query, or identifier data in the appropriate read mode; not

used for status register reads. High-Z when the device is deselected (CE#=high),

outputs are disabled (OE#=high), or Byte#= Low.

CE[2:0] Chip Enables (input): CE[2:0] activate the device's control logic, input buffers,

decoders, and sense amplifiers. Multiple chip enable signals allow switching

between several devices without additional decoding logic. For these examples

design CE1 and CE2 are tied to ground. CE0-low enables the device. CE0-high

disables the device, reducing power consumption to standby levels. Chip enable

signals must remain asserted during read and write accesses.

OE# Output Enable (input): An active low signal, OE#-low activates the device's outputs

during a read operation. This signal must remain inactive (high) during write

operations.

WE# Write Enable (input): An active low signal, WE# controls writes to the Command

User Interface, write buffer, and flash array blocks. Address and data are latched on

the rising edge of WE#. WE# must remain inactive (high) during read operations,

and must toggle between consecutive writes.

RP# Reset/Power Down (input): Active low, RP#-low resets internal automation and

puts the device in power-down mode. RP#-high enables normal operation. When

driven low, RP# inhibits write operations providing data protection during power

transitions. Upon exiting from reset, the device defaults to read array mode with

page mode enabled.

BYTE# Byte Enable (input): Active low, BYTE#-low places the device in x8 mode. All data

is then input or output on DQ[7:0], while DQ[15:8] is High-Z. Address bit A0

selects between the high and low byte. BYTE#-high places the device in x16 mode.

This turns off the A0 input buffer and A1 becomes the lowest-order, word address

bit.

4.2 Microprocessor SRAM Unit Interface

The IXP12x0 contains an SRAM Unit used to interface to a variety of memory types. The external

memory bus supports SSRAM, BootROM, and memory mapped slow port devices such as Digital

to Analog Converters (DACs) (see Figure 1, "IXP12x0 SRAM Unit Interface Configuration).

AP-765

7

BootROM devices include ROM, EPROM, and asynchronous flash memory. Memory size and

configuration are programmable through the IXP12x0's SRAM Control and Status Registers

(CSR's).

Figure 1. IXP12x0 SRAM Unit Interface Configuration

A7988-01

A[18:0]

SP_CE#

SLOW_RD#

DQ[31:0]

SLOW_EN#

SLOW_WE#

SWE#

Decode

Logic

CE[n]#

CE[0]#

SOE#

ce#

we#

oe#

addr

data

SSRAM

256Kx32

ce#

ce1#

ce2

we#

oe#

addr[17:0]

d[31:0]

CE#[0:3]

Tranceiver

dir

en b[31:0]

a[31:0]

Buffer

Slow Port

Device

SLOW_EN#

SSRAM

Memory Mapped

Slow Port Devices

Slow Interface

Logic

IXP1200

SRAM Unit

SP_DIR/LOW_EN#

ce#

ce#

ce#

CE#[3:0]

SLOW_EN#

ce#

ce#

we#

oe#

addr[18:0]

d[15:0]

ce#

ce#

ce#

A[18:0]

DQ[31:16]

A[18:0]

Shown: 4 Mbyte = 256 Kbyte devices by

4 bytes/device x 4 devices

BootROM

Flash

512x16

addr[18:0]

d[15:0]

ce#

we#

oe#

DQ[15:0]

HIGH_EN#/RDY#

rdy

Flash

512x16

(Optional) Upper 16 data bits for

the 32-bit BootROM interface

Shown: Maximum BootROM configuration

8M Byte =512K byte devices by

2 bytes/device x 8 devices

Minimum BootROM configuration (not shown)

512K Byte = 128K byte devices x 2

bytes/device

GPIO[3] at reset

low = 32-bit interface

high = 16-bit interface

clkSCLK

SCLKIN Required for Flow Thru devices)

AP-765

8

The following IXP12x0 external memory interface signals are used in this design.

A[18:0] Address Bus (output).

DQ[31:0] Data Bus (bi-directional).

CE#[3:0] SRAM Bus chip enable (output). Internally decoded from SRAM

address. Valid during SRAM and BootROM accesses.

SLOW_EN# Slow device enable (output): Active-low, SLOW_EN# indicates

access to slower devices, (BootRom or SlowPort). When high,

indicates access to faster SRAM.

SLOW_RD# (output) BootROM interface read enable.

SLOW_WE# (output) BootROM interface write enable.

LOW_EN#/DIRW# (output) Low-order SRAM bank enable and buffer direction select for slow

interface. When used as the buffer direction select: 0 = Write and 1

= Read.

4.3 Interface Considerations

This design example uses two 28F320J3A flash memory devices interfaced with the IXP12x0 in a

x32 data bus configuration. Other bus speeds and memory sizes could be implemented by

modifying the design.

This interface design does not include all information regarding system initialization, interrupt

control, exception handling, or other peripheral device operations. External devices signals/pins

should be asserted or deasserted as necessary for desired device operation. Also, proper power

supply voltages must be applied in accordance with the latest datasheet information. Be sure to

read all applicable documentation (e.g., datasheets, user manuals, errata sheets) before attempting

this interface.

4.4 Hardware Connections

Figure 2, "Block Diagram shows two 28F320J3A devices connected to the Intel IXP12x0 Network

processor; SRAM Unit.

The BootROM address space supports up to 8 Mbytes (64Mbits) of Flash or EPROM. The

BootROM is mapped to the StrongARM* core physical address 0x00. At start-up (reset), IXP12x0

begins fetching and executing instructions from address 0x00. The logic state on the GPIO(3) pin

at power-up configures the size of the data bus. GPIO(3) is shown grounded to configured the

IXP12x0 for a 32-bit data bus. Data byte connections are arranged for little-endian operation.

The SRAM Unit data lines DQ[15:0] are connected to the first flash's data lines DQ[15:0]. The

SRAM Unit data lines DQ[31:16] are connected to the second flash's data lines DQ[15:0]. External

buffers are recommended to prevent excessive loading on the data bus.

AP-765

9

External logic controls the buffer direction using the LOW_EN#/DIRW# signal. The Slow_WE#

and Slow_RD# signals from the SRAM Unit are connected directly to the flash WE# and OE#

signals, respectively.

NOTES:

1. Hardware connections interfacing two 32 Mbit memory devices.

2. IXP12x0 does not support Byte mode. Tie BYTE# high, and connect FlashA[1] to IXP A[0].

3. A0 is not used when in x16 mode.

The SRAM Unit address lines A[18:0] are connected to the flash address lines A[19:1] using

buffers to minimize loading of the IXP12x0 address bus. The remaining two address lines off the

flash are connected to the SRAM Unit chip enable signals via external logic. The 8Mbyte memory

configuration used for the SRAM Unit chip selects are provided in Figure 3.

Figure 2. Block Diagram

A[18:0]

DQ[31:0]

SLOW_WE#

SLOW_EN#

RST_IN#

28F320J3A

Intel StrataFlash.

Memory

D[15:0]

CE0

OE#

WE#

RP#

A[19:1]

Vcc

INTEL

IXP12x0

CE#[1]

A21

A20

SLOW_RD#

BYTE#

GPIO3

Note 1

Notes:

1) Hardware connections interfacing two 32Mbit memory devices.

2) IXP12x0 does not support Byte mode. Tie BYTE# high, and connect Flash A[1] to IXP A[0].

3) A0 is not used when in x16 mode

Note 3Buffer

LOW_EN#DIRW#

CE#[3]

CE#[0]

CE#[2]

DIR

ENA

1 = Read

0 = Write

1 = SRAM

0 = Flash or SlowPort

Note 2

System RST

CE[2:1]

AP-765

10

5.0 Register Settings

The SRAM Unit contains registers used to configure the external memory interface. The

SRAM_Control and Status Registers (CSRs), SRAM_SLOW_CONFIG Register, and

SRAM_BOOT_CONFIG Register settings are described in the following section. Register bit

fields that affect memory interface operations with the 28F320J3A are discussed; all other bit fields

should be programmed as necessary to ensure proper device operation.

5.1 SRAM_CSR Register (CSRs)

The CSR Register Bit 14 (8MF) configures the IXP12x0 for use with an 8 MB flash ROM

configuration (4 banks of 2 MB each. All banks do not have to be populated). Address bits 19 and

20 control the CE#[3:0] pins (see Figure 3, "Memory Configurations). The SRAM_CSR register

settings are listed Table 1.

Figure 3. Memory Configurations

A7989-01

20 0

Internal address

15

External address A[x:0]

A[15:0] = wo/device select 256K byte/64K LW address

A[14:0] = w/device select 128K byte/32K LW address

16171819

Chip Enable LOW_EN#, HIGH_EN# (Optional)

0: LOW_EN# = 0, HIGH_EN# = 1

1: LOW_EN# = 1, HIGH_EN# = 0

14

1M Byte Maximum Configuration

(256K bytes address x 4 devices)

(128K bytes address x 2 banks x 4 devices)

20 0

Internal address

1516171819

2M Byte Maximum Configuration

(512K bytes x 4 devices)

(256K bytes x 2 banks x 4 devices)

20 0

Internal address

171819

4M Byte Maximum Configuration

(1M byte address x 4 devices)

(512K byte address x 2 banks x 4 devices)

20 0

Internal address

171819

8M Byte Maximum Configuration

(2M byte address x 4 devices)

(1M byte address x 2 banks x 4 devices)

16

Chip Enable CE#[3:0]

00 CE#[3:0] = 1110

01 CE#[3:0] = 1101

10 CE#[3:0] = 1011

11 CE#[3:0] = 0111

Intel. StrongARM*

Byte Address20 016171819 122 21

Longword

Address

Intel StrongARM

Byte Address20 01819 122 21

Longword

Address

Intel StrongARM

Byte Address20 019 122 21

Longword

Address

Intel StrongARM

Byte Address20 016171819 122 21

Longword

Address

Chip Enable LOW_EN#, HIGH_EN# (Optional)

0: LOW_EN# = 0, HIGH_EN# = 1

1: LOW_EN# = 1, HIGH_EN# = 0

Chip Enable LOW_EN#, HIGH_EN# (Optional)

0: LOW_EN# = 0, HIGH_EN# = 1

1: LOW_EN# = 1, HIGH_EN# = 0

Chip Enable LOW_EN#, HIGH_EN# (Optional)

A[18] = 0: LOW_EN# = 0, HIGH_EN# = 1

A[18] = 1: LOW_EN# = 1, HIGH_EN# = 0

Chip Enable CE#[3:0]

00 CE#[3:0] = 1110

01 CE#[3:0] = 1101

10 CE#[3:0] = 1011

11 CE#[3:0] = 0111

Chip Enable CE#[3:0]

00 CE#[3:0] = 1110

01 CE#[3:0] = 1101

10 CE#[3:0] = 1011

11 CE#[3:0] = 0111

Chip Enable CE#[3:0]

00 CE#[3:0] = 1110

01 CE#[3:0] = 1101

10 CE#[3:0] = 1011

11 CE#[3:0] = 0111

External address A[x:0]

A[16:0] = wo/device select 512K byte/128K LW address

A[15:0] = w/device select 256K byte/64K LW address

External address A[x:0]

A[17:0] = wo/device select 1M byte/256K LW address

A[16:0] = w/device select 512K byte/128K LW address

External address A[x:0]

A[18:0] = wo/device select 2M byte/512K LW address

A[17:0] = w/device select 1M byte/256K LW address

* Other brands and names are the property of their respective owners.

AP-765

11

Table 1. SRAM_CSR Register (Sheet 1 of 2)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RES

RLK

RDY

CFT

RES

FLWT

BKW

8MF

4MF

2MF

8MSR

4MSR

2MSR

1MSR

RES

RLAM

IRQ

FIQ

RLRS

RLS

Bits Name Reset R/W Description

31:21 RES 0 R/W Reserved.

20 RLK 0 R/W

Read Lock Order. If set, when a read_lock command is placed into the

read_lock fail queue, all subsequent read_lock commands are placed into

the read_lock fail queue regardless of whether or not the memory address is

entered in the read_lock CAM. This ensures that all read_lock commands

are serviced in the order in which they were issued.

19 RDY 0 R/W

Slow Port RDY Enable. When set, the internal clock that determines the

Slow Port timing is paused at the cycle count in

SRAM_SLOW_CONFIG[23:16] until the RDY# pin is asserted. When clear,

the HIGH_EN#/RDY pin acts as a high enable pin.

18 CFT 0 R/W

Command FIFO Test Enable. Used for testing purposes by Intel and must be

set to zero. Allows the StrongARM Core to access the command FIFO for

testing. When set, the command FIFO is mapped to StrongARM Core

address space 0x3800 0200 - 3800 03FC and Microengine address space

0x60 0080 - 60 00FF.

17 RES 0 R/W Reserved.

16 FLWT 0 R/W

Flowthrough SRAM Enable. This bit must be set when using flowthrough

SRAMs that have a pipe delay of 2 clock cycles. This bit should be cleared

when using pipeline SRAMs that have a pipe delay of 3 clock cycles.

15 BKW 0 R/W

Bank Switch Wait Enable. When set, this bit enables a wait state to be

inserted when switching between the 8 SRAM banks. This bit must be set

when using SRAMs that have a slower output disable time than output

enable time.

14 8MF 0 R/W

When set, configures the IXP1200 for use with an 8 MB flash ROM

configuration (4 banks of 2 MB each. All banks do not have to be populated).

Address bits 19 and 20 control the CE_L[3:0] pins.

13 4MF 0 R/W

When set, configures the IXP1200 for use with a 4 MB flash ROM

configuration (4 banks of 1 MB each. All banks do not have to be populated).

Address bits 18 and 19 control the CE_L[3:0] pins.

12 2MF 0 R/W

When set, configures the IXP1200 for use with a 2 MB flash ROM

configuration (4 banks of 512 KB each. All banks do not have to be

populated). Address bits 17 and 18 control the CE_L[3:0] pins.

11 8MSR 0 R/W

When set, configures the IXP1200 for use with an 8 MB SRAM configuration

(8 banks of 1 MB each. All banks do not have to be populated). Internally,

address bits 19 and 20 control the CE_L[3:0] pins and address bit 18

controls the HIGH_EN_L and LOW_EN_L pins.

10 4MSR 0 R/W

When set, configures the IXP1200 for use with a 4 MB SRAM configuration

(8 banks of 512 KB each. All banks do not have to be populated). Internally,

address bits 18 and 19 control the CE_L[3:0] pins and address bit 17

controls the HIGH_EN_L and LOW_EN_L pins.

9 2MSR 0 R/W

When set, configures the IXP1200 for use with a 2 MB SRAM configuration

(8 banks of 256 KB each. All banks do not have to be populated). Internally,

address bits 17 and 18 control the CE_L[3:0] pins and address bit 16

controls the HIGH_EN_L and LOW_EN_L pins.

8 1MSR 0 R/W

When set, configures the IXP1200 for use with a 1 MB SRAM configuration

(8 banks of 128 KB each. All banks do not have to be populated). Internally,

address bits 16 and 17 control the CE_L[3:0] pins and address bit 15

controls the HIGH_EN_L and LOW_EN_L pins.

7:5 RES 0 R/W Reserved.

AP-765

12

5.2 SRAM_SLOW_CONFIG Register

The BootRom timing parameters are programmed via the SRAM_SLOW_CONFIG and

SRAM_BOOT_CONFIG SRAM CSR's.

BootROM Cycle Count (BCC) Bits 15:8 is the initial value loaded into an internal counter that

determines the total cycle time in TCLK's for accesses to the BootROM in the SRAM Unit address

space. The BootROM cycle time equals (BCC+1)/(core clock frequency) MHZ. The LSB of the

cycle count is hard coded to 1 to produce odd cycle count values. The SRAM_SLOW_CONFIG

register settings are listed in Table 2.

4 RLAM 0 R/W

StrongARM Read Lock Achieved Mask. When set, this bit masks the

interrupt generated by the StrongARM read lock achieved status bit.

3 IRQ 0 R/W

IRQ Enable. When set, enables the StrongARM IRQ interrupt to be

generated by either the Read Lock Achieved Status bit or the Read Lock

Retry Status bit being set. The read lock achieved status can be masked

using the Read Lock Achieved Mask bit in the SRAM CSR.

2 FIQ 0 R/W

FIQ Enable. When set, enables the StrongARM FIQ interrupt to be

generated by either the Read Lock Achieved Status bit or the Read Lock

Retry Status bit being set. The read lock achieved status can be masked

using the Read Lock Achieved Mask bit in the SRAM CSR.

1 RLRS 0 R/W

StrongARM Read Lock Retry Achieved Status. If an StrongARM read lock

attempt fails due to the address already being locked or if the maximum of 8

read locks are already taken. The failed read lock will go onto the read lock

retry queue. This bit is set when the failed read lock is successfully

completed. This bit can be cleared by writing it with a value of 1.

0 RLS 0 R/W

StrongARM Read Lock Achieved Status. This bit returns the status of the

last read lock attempt made by the StrongARM Core. When set, the last

read lock attempt was successful. When clear, the last read lock attempt

failed.

Table 1. SRAM_CSR Register (Sheet 2 of 2)

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RES

RLK

RDY

CFT

RES

FLWT

BKW

8MF

4MF

2MF

8MSR

4MSR

2MSR

1MSR

RES

RLAM

IRQ

FIQ

RLRS

RLS

Bits Name Reset R/W Description

Table 2. SRAM_SLOW_CONFIG Register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RES BCC SCC

Bits Name Reset R/W Description

31:16 RES 0 R/W Reserved.

15:8 BCC 0x23 R/W

BootROM Cycle Count. This is the initial value loaded into an internal

counter that determines the total cycle time for accesses to the BootROM in

the SRAM Unit address space. The BootROM cycle time equals (BCC+1)/

(core clock frequency). The LSB of the cycle count is hard coded to 1 to

produce odd cycle count values.

7:0 SCC 0x41 R/W

SRAM Slow Port Cycle Count. This is the initial value loaded into an internal

counter that determines the total cycle time for accesses to the SRAM Slow

Port memory space in the SRAM Unit address space. The SRAM Slow Port

cycle time equals (SCC+1)/(core clock frequency). The LSB of the cycle

count is hard coded to 1 to produce odd cycle count values.

AP-765

13

5.3 SRAM_BOOT_CONFIG Register

When used with the SRAM_SLOW_CONFIG register, the SRAM_BOOT CONFIG register sets

the timing for BootROM in SRAM space. The SRAM_BOOT_CONFIG register settings are listed

in Table 3.

Table 3. SRAM_BOOT_CONFIG Register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BRWA BCEA BRWD BCED

Bits Name Reset R/W Description

31:24 BRWA 0x1C R/W

BootROM Read/Write Assert. This value is used to create the BootROM

SLOW_RD#/SLOW_WE# assert time as measured after the start of the

BootROM cycle. The SLOW_RD#/SLOW_WE# signal is asserted (BCC -

BRWA+1) cycles after the start of the BootROM access cycle. BCC

(BootROM cycle count) is defined in the SRAM_SLOW_CONFIG register.

23:16 BCEA 0x20 R/W

BootROM SLOW_EN# Assert. This value is used to create the BootROM

SLOW_EN# assert time as measured after the start of the BootROM cycle.

The SLOW_EN# signal is asserted (BCC - BCEA+1) cycles after the start of

the BootROM access cycle. BCC (BootROM cycle count) is defined in the

SRAM_SLOW_CONFIG register.

15:8 BRWD 0x09 R/W

BootROM Read/Write Deassert. This value is used to create the BootROM

SLOW_RD#/SLOW_WE# deassert time as measured after the start of the

BootROM cycle. The SLOW_RD#/SLOW_WE# signal is deasserted (BCC -

BRWD+1) cycles after the start of the BootROM access cycle. BCC

(BootROM cycle count) is defined in the SRAM_SLOW_CONFIG register.

7:0 BCED 0x04 R/W

BootROM SLOW_EN# Deassert. This value is used to create the BootROM

SLOW_EN# deassert time as measured after the start of the BootROM

cycle. The SLOW_EN# signal is deasserted (BCC - BCED+1) cycles after

the start of the BootROM access cycle. BCC (BootROM cycle count) is

defined in the SRAM_SLOW_CONFIG register.

AP-765

14

6.0 Bus Operations and Timings

For the following discussion on bus operations and timings, refer to Table 4, "Read Operation

Definitions" and Table 5, "Write Operation Parameter Definitions" for a description of all the flash

memory timings shown in the waveforms. Refer to Table 2, "SRAM_SLOW_CONFIG Register"

on page 12 and Table 3, "SRAM_BOOT_CONFIG Register" on page 13 for a description of all the

processor timings.

For additional information regarding the individual components presented in this design example,

consult the appropriate documents as listed in Appendix A, "Additional Information" on page 17.

Note that memory timings start with R (for Read) or W (for Write). Parameters in parentheses

represent the register bit names of the SRAM Unit register settings, which determine the clock

delays required.

Table 4. Read Operation Definitions

# Symbol Parameter Definition

R1 tAVAV Read/Write Cycle Time

R2 tAVQV Address to Output Delay

R3 tELQV CEx to Output Delay

R4 tGLQV OE# to Non-Array Output Delay

R7 tGLQX OE# to Output in Low Z

R8 tEHQZ CEx High to Output in High Z

R9 tGHQZ OE# High to Output in High Z

R10 tOH

Output Hold from Address, CEx, or OE# Change,

Whichever Occurs First

Table 5. Write Operation Parameter Definitions

# Symbol Parameter Definition

W2 tELWL (tWLEL) CEx(WE#) Low to WE# (CEx) Going Low

W3 tWP Write Pulse Width

W4 tDVWH (tDVEH) Data Setup to WE# (CEx) Going High

W5 tAVWH (tAVEH) Address Setup to WE# (CEx) Going High

W7 tWHDX (tEHDX) Data Hold from WE# (CEx) High

W8 tWHAX (tEHAX) Address Hold from WE# (CEx) High

W9 tWPH Write Pulse Width High

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15

6.1 Asynchronous Single Reads

Figure 4, "Asynchronous Single--Word Read shows the bus timings for an initial read following a

reset. Read accesses after a reset are always asynchronous single reads. Non-array (register) reads

are performed in this mode, as well.

Figure 4. Asynchronous Single--Word Read

R9

R8R10

R4

R2

R3

R7

BCC - BRWD +1

BCC - BRWA +1

BCC - BCED +1

BCC - BCEA +1

R1

BCC

R1

BCC

SCLK

A[18:0]

SLOW_EN#

SLOW_RD#

SLOW_WE#

DQ[31:0]

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16

6.2 Asynchronous Writes

Figure 5 shows the bus timings for an asynchronous write to the 28F320J3. Parameters in

parentheses represent the register bit names of the SRAM Unit register settings, which determine

the clock delays required.

7.0 Summary

The 3 Volt Intel StrataFlash.

Memory product line provides reliable two-bit-per-cell technology.

Offered in 128-Mbit (64-Mbyte), 64-Mbit (8-Mbyte), 32-Mbit (4-Mbyte) densities for increased

flexibility, with features for mainstream performance at low costs. Providing an excellent option

for both code and data applications where high density and low cost are required.

Ultimately, the flexible interface of the 3 Volt Intel StrataFlash.

Memory components give

designers a simple interface with processors, which helps to reduce power consumption, decrease

costs and increase overall system reliability by eliminating the need for additional interface

components.

Figure 5. Asynchronous Write

W7

W4

W9W9

W3

W5

W8

BCC - BRWD +1

W3

W2

BCC-BRWA +1

BCC - BCED +1

BCC - BCEA +1

BCCBCC

SCLK

A[18:0]

SLOW_EN#

SLOW_RD#

SLOW_WE#

DQ[31:0]

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17

Appendix A Additional Information

Order Number Document/Tool

290667

3 Volt Intel StrataFlash.

Memory; 28F128J3A, 28F640J3A, 38F320J3A (x8/

x16) Datasheet

278298 Intel.

IXP1200 Network Processor Datasheet

278303 Intel.

IXP1200 Network Processor Family Hardware Reference Manual

278304

Intel.

IXP1200 Network Processor Family: Microcode Programmer's

Reference Manual

298130 3 Volt Intel StrataFlash.

Memory 28F128J3A, 28F640J3A, 28F320J3A

Specification Update

297859 AP-677 Intel StrataFlash.

Memory Technology

292222 AP-664 Designing Intel StrataFlash.

Memory into Intel. Architecture

251212 AP-757 Schematic Review Checklist for 3 Volt Intel StrataFlash.

Memory

292221 AP-663 Using the Intel StrataFlash.

Memory Write Buffer

292218 AP-660 Migration Guide to 3 Volt Intel StrataFlash.

Memory

250260 AP-751 System Design Considerations When Designing with Intel.

Flash

292204 AP-646 Common Flash Interface (CFI) and Command Sets

292172 AP-617 Additional Flash Data Protection Using VPP, RP#, and WP#

NOTES:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools.

3. For the most current information on Intel flash products, visit our website at http://developer.intel.com/

design/flash/.

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