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Line drivers thrive in ADSL2/ADSL2+ designs

Posted: 16 Dec 2003     Print Version  Bookmark and Share



By Kaveh Parsi

Director of Marketing

DSL Line Drivers


Michael Wong

Director of Applications


Elantec Product Group

Intersil Semiconductor Inc.


sipate the largest percentage of

power in a central office (CO)


tems. Thus, to optimize line

driver designs for power effi-

ciency and data rates required,

engineers must carefully select

power supplies, line termina-

tion, transformer ratio and a

line driver with superb linear


In this article, we will

present a method for calculat-

ing power dissipation while

also discussing the trade-offs

between supply voltage and

performance. During this dis-

cussion, we will show how the

24V line driver offers the best

solution for low-power and

cost-effective designs in a field

of line drivers that ranges from

5V to 48V.

Signal chain

The DSL signal chain is com-

prised of a DSP, analog front-

end (AFE), line driver and

transformer (Figure 1). CO

line cards such as those used in

a DSLAM try to pack as many

DSLs as possible on a card to

gain the lowest cost per port for

a system. Low power and small


criteria to enable 48, 72 and 96

ports on a line card. Since the

line driver and hybrid filter dis-

sipate the largest percentage of

the power and occupy a signifi-

cant portion of the footprint,

careful consideration of the

type of line driver and its asso-

ciated supply voltage is neces-

sary to optimize power, space

and costs for the line card.

In the DSL signal chain, the

line driver amplifies the signal

from the AFE and drives the

high current load of the trans-

former coupled telephone line.

There are four main criteria

that designers need to consider

when selecting a line driver.

These include superb linear

performance at high output

voltage swing, less than

800mW power dissipation,

small footprint and low cost.

The class A/B current feedback

amplifier has been the domi-

nant architecture used since it

can provide excellent specifica-

tions for all criteria.

Let us take a closer look at

the trade-offs by analyzing the

driver section of the signal

chain. The basic voltage, cur-

rent and power requirements

for driving the line are pre-

sented. We will also discuss the

various options for supply volt-

age and the effects on process

technology and cost.

CO downstream specs

For full-rate discrete multitone

(DMT) signaling, the peak out-

put line power is rated +20dBm

while POTS line impedance is

set at 100. By designing with



care of any clipping of the sig-

nal, we can optimize for lower

power dissipation in the line


From output line power and

line impedance, we can calcu-

late average output line voltage

swing and current:

20dBm = 10 log (Pout



= 20dBm=100mW


= (Vout

-rms )2/Rload





-rms = 3.16V

The telephone line is a

twisted pair conductor and is

driven with differential signal-

ing to minimize common mode

noise from cross talk in the

bundle. The line peak-to-peak


calculated using the CR or

peak-to-average ratio (PAR).

CR = 20 log (PAR) = 14.5dB

Line drivers thrive in ADSL2/ADSL2+ designs

PAR = 5.3


-ptp = Vout

-rms * PAR

= 3.16*5.3 = 16.76V


-ptp diff = Vout

-ptp *2

= 33.52V

Based on the above specifi-

cations, the CO ADSL output

peak-to-peak voltage swing re-

quirement on the differential

twisted pair cable is 33.52V.

Output peak current can then

be calculated by dividing the

peak-to-peak output voltage by

the 100 line impedance. In

the case of ADSL2+, this

equates to 167.6mA.

The conventional differen-

tial driver pair consists of two

amplifiers to transmit a differ-

ential signal. Figure 2 shows a

typical differential driver cir-

cuit configuration. As calcu-

lated previously, the peak-

to-peak output voltage across

the line is 33.52V while peak

line current is 167.6mA. On the

DSL chipset

DSP AFE Hybrid Transformer




Power system DC:DC
















-12V Vee







1 : N











Figure 1: CO line cards try to pack as many DSLs as possible on a card to gain the lowest cost per port for a system.

Figure 2: The conventional differential driver pair consists of two amplifiers to transmit a differential signal.

driver side, the output current

and voltage swing are deter-

mined by the transformer turns

ratio N and back termination

resistor value Rterm.

Other key specifications of

the differential pair driver and

receiver are symmetrical dy-

namic response, wide band-

width, low differential phase

and gain, flexible enable/dis-

able and power cut back mode

operation, high output current

drive and low total harmonic


Proper termination of the

line with impedance matching

resistors Rterm are also critical.

For 100 percent back match,

Rterm isequaltoRload/2andthus

will drop halfoftheoutputvolt-

age from the line driver and re-

duce efficiency by 50 percent

for delivering the signal power

to the line. To minimize the ter-

mination resistor value, active

termination circuit technique

is often used to synthesize the

line impedance with a small re-

sistor and positive feedback.

Figure 3 shows the active

termination circuit. The posi-

tive feedback circuit has the ef-

fect of gaining up the back

match resistor value as seen to

the load across V0+ and Vo- by a

synthesis factor Ks.

To avoid oscillation caused

by excessive positive feedback,

the optimum synthesis factor

for most designs is five. With

Ks=5, 100 line impedance

and transformer ratio of N, the

line driver termination resis-

tance can be written as

2RBM=100/N2Ks, and RBM

=10 for a 1:1 transformer ra-


power calculations to see how

the output swing, supply volt-

age and termination affect the

power dissipation of the line


Power dissipation calculation

The power dissipation of the

line driver exclusive of the

power delivered to the line is

composed of two parts: a quies-

cent power (Pdq) and an output

power (Pdo).

Pdriver= Pdq + Pdo

Pdq= Vs*Iq

Pdo= (Vs - Vout-rms) * Iout-rms

Pdriver= Vs*Iq + (Vs - Vout-rms) *


Total Pconsumption= Pdriver + Pline

= Pdiss + 100mW

In the equations above, Vs is

the supply voltage and Iq is the

quiescent bias current of the

driver. Intuitively, Pdq is the

power required to keep the am-

plifiers biased and ready even

when not driving a signal. Pdo is

the power dissipated in the

driver from resistive drops in

the output stage as it delivers

the rms output load current.

These drops are revealed in a

driver data sheet as headroom

required for driving a linear


The ability to swing close to

the rail is important because

the peak output voltage is the

rms output voltage times the

CR. In the design of the circuit

in Figure 3, the maximum lin-

ear output swing from the

driver is used to deliver the

peak signal voltage. Thus, the

closer a driver can swing to its

supply rail, the less headroom

required and the less power dis-

sipated in the driver.

In the above analysis, it is

evident that the bias current is

a critical part of power dissipa-

tion. Increasing or decreasing

the bias current can improve or

distort the linear performance


feature in a DSL driver is the

ability to finely adjust the bias

current and achieve the right

level of linear performance, yet

minimize quiescent power


Transformer, supply

voltage effects

As mentioned above, the turns


portant design element as well.


stage in the signal chain. If the

driver cannot provide adequate

swing from the given supply to

reach the desired Vout peak-to-


tio is selected to gain up the sig-

nal to the line. If a driver is se-

lected with high enough sup-

plies to create more than the re-

quired output signal, the trans-

former ratio is designed to at-

tenuate the voltage swing down

to the proper level on the line.

Thus, the transformer can be

used to accommodate line driv-

ers with supplies ranging from

5V to 48V if desired.

As the supply is lowered, the

load current required from the

driver is increased. Hence,

lower supply voltage drivers re-

quire large output stages (die

area, package and footprint)

and large quiescent currents to

drive the associated internal

capacitance of the output

stages. In addition, the trans-


the drive signal serves as an at-

tenuator for the receive signal

and makes the SNR for the re-

ceive path smaller by approxi-

mately a factor of N. Con-


require smaller output stages

and less quiescent current.


higher the voltage, the better

the efficiency. Let us recall that

the headroom for the amplifier

must be sufficient as well. For

high-voltage drivers on high-

voltage processes, the transis-

tors and die area are necessar-

ily large, and IC design rule




















Figure 3: Differential line driver with active termination.

Table 1: DSL driver comparison based on supply voltage requirement.

spacing is such that device ele-

ments are increased in size to

withstand high voltages and as-

sociated fields. The ratio of

headroom to output swing

needs to be optimized, as well

as the ability to produce a high-

voltage amplifier with suffi-

cient bandwidth and flat gain

response of 4MHz to cover the

ADSL to ADSL2+ frequency

band. The bandwidth and gain

must be achieved without com-


or noise.

The transistors in a high-

voltage process are larger, and

the capacitances are higher.


escent power required to drive

the capacitances can again be-

come a real challenge. These


to resurface in processes over

30V. For example, today's 48V

line drivers aimed at direct bat-

tery applications require 5V

headroom and dissipate over

150mW just in quiescent

power. This type of devices is

challenged to meet the band-

width and out-of-band noise re-

quirements in the ADSL2

power spectral density masks.

As discussed, the trade-offs

for power, noise and footprint

lead us to a group of amplifiers

in the 15V to 30V supply range

that are the most suitable for

DSL applications. If we look at

the mid-region of this supply

range and analyze the power

optimization, we can deter-

mine the best supply voltage.

From the earlier analysis,

recall that we are required to

provide a 33.52V peak-to-peak

differential voltage across the

telephone line on the second-

ary side of the transformer. It is

desirable to keep the trans-

former ratio at 1:1 from the


It eliminates transformer

mismatch error, and the result

is a consistent and simple



nation and select a 20 percent

termination resistor (Ks=5) to

minimize the power loss across

the termination resistors. We

can calculate the peak output

voltage swing required at the

amplifier outputs as

Vswing=1.2*33.52= 40.24V

peak-to-peak differential. In

terms of single-ended signal-

ing, this is 20.12V or 1 10.06--

which can be achieved from an

amplifier with less than 2V

single-side headroom from

112V supply.

There are many bipolar

dielectrically-isolated current

feedback amplifiers available

with superb linearity that meet

this criteria. What distin-

guishes the best from the pack

is the ability to achieve less

quiescent current and smaller

die size. As discussed, quies-

cent current times supply volt-

age comprises the second part

of the power dissipation equa-

tion, and less bias current can

result in lower total power


Cost concerns

One thing designers must ask

here is "What about cost?"

There is an argument that run-



save the cost of providing regu-


that the battery voltage is noisy

and not well regulated. The bat-


72V in the system. When taking

into account this variance and

the inherent bandwidth limita-

tion that do not allow for active

termination or ADSL2 and

ADSL2+ operation, the design

results in a high power dissipa-

tion for the line driver. Also, the

need for expensive high-voltage

capacitors, a supply line filter


print offset any cost advantages

claimed by such a solution.

In comparison, the class A/B

current feedback amplifiers

running at 112V or single +24V

supplies achieve very low

power--greater than ADSL2+


sive components. As shown in

the middle column of Table 1,

today's leading DSL drivers can

achieve better than ADSL2+

bandwidths while consuming

only 700mW total power and

occupying less than 10mm of

package footprint per port.

Smaller packages are generally

less expensive, and thus lead to

lower overall product costs.

DSL is a technology that can

deliver more than data through

the telephone lines. The reality

is that we are closer than ever

to the delivery of voice, data

and video--the "triple play."

ADSL2 and ADSL2+ standards

are capable of up to 24Mbps

data rates. These technologies

are key to providing the neces-

sary bandwidth for effective


standards require higher fidel-


THD) from the line drivers in

order to pack more bits into the

DSL signaling.

We have shown that the high

output current class A/B CFA

amplifier running from 24V

power supplies with built-in

power selection offers the best

performance with regard to

power, linearity, ease of use and


of specialized line drivers have

the proven capability to provide

the performance to push DSL


for 50Mbps transfer rates.

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