Global Sources
EE Times-India
 
EE Times-India > EDA/IP
 
 
EDA/IP  

Timing closure: Hybrid optimization to the rescue

Posted: 16 Aug 2004     Print Version  Bookmark and Share

Keywords:timing  closure  hybrid  optimization  asic 

Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure.

View the PDF document for more information.



Comment on "Timing closure: Hybrid optimization ..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top