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FCRAM 101: Understanding the basics

Posted: 01 Oct 2004     Print Version  Bookmark and Share

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By Kevin Kilbuck

Director of Memory Engineering

Toshiba America Electronic

Components

E-mail: kevin.kilbuck@

taec.toshiba.com

Historically, DRAMs have been

developed largely by taking the

needs of the PC market into

consideration. Because of this

influence, designers of other

applicationshavebeenforcedto

use the "PC DRAM" regardless

ofwhetherornotitwassuitable

for their application. Specifi-

cally, these PC DRAMs have

createdbottlenecksfordevelop-

ers of networking equipment

trying to deliver 2.5Gbps data

rates and beyond.

Fortunately, solutions are

on the horizon. Several DRAM

architectures optimized for the

needs of networking equip-

ment designs are now hitting

the market.

Fast-cycle RAM (FCRAM), a

technology co-developed by

Toshiba Corp. and Fujitsu Ltd,

is one solution quickly emerg-

ing for the networking design

community. The primary ben-

efits of FCRAM include the

combination of DRAM densi-

ties with random cycle perfor-

mance approaching SRAM

speeds; its proprietary core

technology that achieves fast

random access time (tRAC) and

random cycle time (tRAC); and

anarchitecturethatoffersshort

(tRAC) and (tRC), as well as high

bandwidth combined with a

conventional DDR interface

using a more cost-effective

DRAM technology.

Traditional approach

Inthepast,DRAMperformance

enhancements have been fo-

cusedonarchitecturemodifica-

tions, such as increasing the

peakbandwidthofthedeviceby

adding high-speed logic to the

I/O. For instance, SDRAMs,

double data rate (DDR)

SDRAMs and Rambus DRAMs

(RDRAMs) all fundamentally

use the same memory core (cell

array)withdifferenthigh-speed

I/O logic implementations to

achieve their respective peak

bandwidth increases.

While these enhancements

can achieve the desired system

performance increases in cer-

tain applications, they may not

realize the same goal in other

applications. For example, in-

creasing DRAM peak band-

width may boost performance

in a PC, where the main

memoryisprimarilyusedtofill

FCRAM 101: Understanding the basics

CPU cache lines. However, it

may have no impact in a net-

working switch environment

that is characterized by short,

random data packets.

Attempts to reduce latency

in these PC-focused DRAMs

have been made by utilizing

multibank schemes. In this sce-

nario, memory banks not cur-

rently being accessed are in a

precharged state, which re-

duces the cycle time if the next

data word to be accessed is con-

tained in one of the precharged

banks.

The primary challenge asso-

ciated with adding more

memory banks is the increase

in the cost of the DRAM. Also,

in the case where the next data

word is within a different row of

the active (non-precharged)

bank, the current access must

be finished and the bank

precharged before the new ac-

cess can begin. None of the pre-

viously mentioned DRAM ar-

chitectures can address this

"same bank" latency.

Enter FCRAM

FCRAM was specifically de-

signed to meet the require-

ments of communication de-

signers. Specifically, this

memory technology was devel-

oped to reduce random cycle la-

tency (random access and cycle

times) while increasing peak

bandwidth. What this really

meansisthattheeffectiveband-

width is superior to the alterna-Figure 1: Combining row pipelining with a fast memory core can make the FCRAM achieve fast random cycle/access times.

DDR-FCRAM

Conventional DRAM

Command,

addresses Command,

addresses

Active command,

row addresses

Precharge

command

Read command,

column addresses

tRAC

tRAC

Data output

Data output

Data output Data output

tRC

tRCtRC

Figure 2: Double data rate fast-cycle RAM command table sets.

First command

Second command (following RDA or WRA command)

H = Logic high, L = Logic low, x = Either low or high, V = Valid (specified) level

BA = Bank address, UA = Upper address, LA = Lower address

Symbol Function CS# FN BA1-0 A14-13 A12-9 AB A7 A6-0

DESL Device deselect H x x x x x x x

RDA Read with auto-close L H BA UA UA UA UA UA

WRA Write with auto-close L L BA UA UA UA UA UA

Symbol Function CS# FN BA1-0 A14-13 A12-9 AB A7 A6-0

LAL Lower address latch H x x V x x x LA

REF Auto-refresh L x x x x x x x

MRS Mode register set L x V L L L V V

tivesincertainapplications,es-

peciallyintheshortdatapacket,

randomenvironmentcharacter-

ized in networking. FCRAM

achieves this by implementing

several architectural enhance-

ments, including three-stage

rowpipelining,fastaccesscore,

simplified DDR feature set and

fast bus turnaround times.

Many DRAMs offer in-

creased performance by using

I/Ologicenhancements,which

can also be referred to as col-

umn pipelining. Hence, the

DRAM column address cycle

time is reduced, achieving fast

burst speed. By using a DDR-

like feature set and interface,

FCRAM also provides this fast

burst capability.

DDR inputs and outputs

data on both edges of the clock,

thus doubling the peak band-

width compared with single

datarateSDRAM.Forexample,

if the clock rate is 133MHz,

SDRAM's data rate and peak

bandwidth are 133MHz and

133Mbps, respectively. Using

the same 133MHz clock, DDR

provides a data rate of 266MHz

and peak bandwidth of

266Mbps, utilizing fundamen-

tally the same process technol-

ogy and memory core design as

SDRAM,withonlyminormodi-

fications to the peripheral I/O

circuitry. FCRAM uses much of

thesamecircuitrymodification

as DDR, such that it can yield

the same peak bandwidth for a

given clock frequency.

Additionally, FCRAM

implements a scheme called

three-stage row pipelining,

which provides a tremendous

improvement in row address

(random) cycle time. By com-

bining row pipelining with a

fast memory core, which is

achieved primarily by segment-

ing the core into smaller sub-

arrays that can be accessed very

fast, the FCRAM can achieve

fast tRAC and tRC. In Figure 1,

designers should note the im-

provement of both tRC and tRAC

for the FCRAM, as well as the

fact that new row addresses

and commands can be provided

to the FCRAM before the cur-

rent cycle is complete (row

pipelining).

The three stages of the

FCRAM's row pipeline are the

address decoder, the memory

array and the I/O buffer. In a

typical DRAM, when a row ad-

dress is provided, the DRAM

must first decode the row ad-

dress, find the location in the

memory array and then read

the data from memory array to

the I/O buffer (or from the I/O

buffer to the memory array in

the case of a write cycle). Be-

causethesefunctionsmusthap-

pen in series, a conventional

DRAM cannot start the next

row address sequence until it

completes the current one by

completing all three stages.

By pipelining these three

functions, FCRAM is able to

begin a new row address access

as soon as the current row ad-

dress is latched in the decoder.

The FCRAM may even start de-

coding a third row address once

thefirstonehasresultedindata

moving from the memory array

to the I/O (or in the opposite

direction in the case of a write

cycle). The result is a random

cycle time of 20ns to 30ns for

FCRAMcomparedwith60nsto

70ns for other types of DRAMs.

Functional difference

In addition to difference in the

pipelining, FCRAM products

provide some key optimiza-

tions over traditional DRAMs

for communications designs.

These functional differences

include:

1. The /RAS, /CAS and /WE

pins are replaced by a func-

tion pin (FN) and two addi-

tional address pins (A13 and

A14). During the first com-

mand (traditional RAS acti-

vation),thestateofFNdeter-

mines a read/write cycle and

the upper (row) address is

latched using A0-A14. The

second command (CAS acti-

vation)latchesthelower(col-

umn) address. Note the

asymmetrical number of

row/column addresses (also

calledbroadsideaddressing),

which is one of the innova-

tions that allows FCRAM to

achievefasterrandomaccess

and cycle times.

2. FCRAM read/write com-

mands always include auto

precharge, which eliminates

read/write commands with-

out precharge and separate

precharge commands, as

well as the multiplexed auto

precharge (A10/AP) pin.

3. FCRAM uses a /PD pin in-

stead of clock enable (CKE)

for power down mode, elimi-

natingtheCKE-to-clocktim-

ing dependencies.

4. FCRAM has variable write

burst length (using A11-

A14), which eliminates the

byte masking command and

the use of a data mask (DM)

pin for every eight I/Os.

5. FCRAM's write CAS latency

(WL) is equal to read CAS la-

tency (RL) minus one cycle.

This provides for much im-

proved read-to-write and

write-to-read bus turn-

around time, compared with

other DRAM types that fix

WL equal to one cycle.

6. Other SDRAM/DDR func-

tions, such as burst stop and

page mode, have been elimi-

nated to simplify FCRAM

controller designs.

Figure2andFigure3high-

light the changes described

above.

FCRAM is a simplified ver-

sionofDDR,yetcloseenoughin

compatibilitywithDDRtoallow

Figure 3: Functional truth table comparison.

Read

or

write

operation

Precharge

Refresh

Power

down

Interrupt

Write data

masking

DDR-FCRAM DDR-SDRAM

RDA

WRA

/PDn-1

H

H

/PD

x

x

/CS

L

L

FN

H

L

A14

UA

UA

A13

UA

UA

N/A

N/A

N/A

N/A

LAL H x H x V V

AutoRefresh H H L x x x

SelfRefresh H L L x x x

PDEN H L H x x x

Variable write burst length supported with A14-11

H = Logic high, L = Logic low, x = High or low, UA = Upper address, V = Valid (specified) level

CKen-1 CKEn /CS /RAS /CAS /WE A10/AP

H x L L H H x

H x L H L H L

H x L H L L L

H x L H L H H

H x L H L L H

H x L L H L L

H x L L H L H

H H L L L H x

H L L L L H x

H x x x x

L H H H x

H x x x x

L V V V x

Active

Read

Write

Read with AP

Write with AP

Precharge

one bank

Precharge

all bank

AutoRefresh

SelfRefresh

Precharge

power down

Active

power down

H L

H L

Byte masking with DM

Yes

DDR-SDRAM

Clock frequency

(MHz)

Bank interleave

Bus

efficiency

(%)

Effective data

X'fer rate

(Mbps/pin)

Effective data

X'fer rate

(Mbps/pin)

67

80

Bus

efficiency

(%)

42

80

Same bank

Peak bandwidth

(Mbps/pin)

100

133

154

200

200

266

308

400

134

177

246

320

80

112

224

292

DDR-FCRAM 80 80

154

200

308

400

246

320

224

292

DDR-FCRAM

8 consecutive data read cycles + 8 consecutive data write cycles + X cycles of turnaround

Figure 4: DDR bandwidth comparison: FCRAM vs. SDRAM. Both the FCRAM and DDR devices used in the calculations have four banks.

a memory controller design to

utilize either device. Assuming

the performance of DDR is ac-

ceptable, this option allows use

ofaPC-focusedDRAMsolution,

although the cost/performance

benefitsofFCRAMshouldmake

it the preferred solution in cer-

tain applications.

FCRAM, DRAM comparison

As mentioned, oftentimes,

DRAM performance numbers

are shown based on peak band-

width, which is simply burst

mode clock speed multiplied by

thenumberofI/Opins,withno

consideration given to random

cycle latency or bus utilization.

For demonstration purposes, a

comparison of FCRAM to DDR

is provided in Figure 4. This

shows the clock frequency of

each device and corresponding

calculation of peak bandwidth.

Todetermineeffectiveband-

width, the designer must deter-

mine the bus efficiency, which

is a measure of the number of

clock cycles when the device is

either inputting or outputting

data (valid data bus cycles) vs.

the total number of clock cycles

for the particular microproces-

sor request. In Figure 4, the

microprocessor request is an

8-word read burst followed by

an 8-word write burst.

Bus efficiency is a function

of the initial latency from the

CPU request to first valid data

word (tRAC for the DRAM);

burst length; precharge "pen-

alty" if the following data word

to be accessed is in the same

bank as the current access (tRC,

which is the sum of the DRAM

precharge time plus tRAC); and

bus turnaround time.

The dependency of bus effi-

ciency on each of these param-

eters is as follows:

1. Bus efficiency is greater for

faster tRAC/tRC;

2. Bus efficiency is greater for

longer bursts;

3. Bus efficiency is greater with

faster bus turnaround time.

The burst length is applica-

tion-dependent, however, tRAC,

tRC and bus turnaround times

are DRAM-dependent, and

FCRAM excels in this regard

due to the aforementioned ar-

chitectural and functional im-

provements over other DRAM

types.

In Figure 4, the bus effi-

ciency is calculated for two

cases. The first case, called

bank interleave, is when con-

secutive data read/write cycles

are always performed from a

precharged bank, that is, a dif-

ferent bank than is currently

being accessed. To elaborate,

the maximum burst length is

four cycles, so a burst of eight

cycles is really a 4-b burst fol-

lowedbyanother4-bburstfrom

aprecharged(different)bankin

this case. On the contrary, the

secondcaseiswherethesecond

4bburstisfromwithinthesame

bank as the first.

As expected, the bus effi-

ciency is considerably worse for

same bank accesses. However,

the degradation for DDR is a

37 percent reduction in bus

efficiency vs. 9 percent for

FCRAM.Simply,FCRAMreally

showsitscapabilitytominimize

the effects of same bank ac-

cesses in applications with a

high degree of randomness.

Determining true bus efficiency

To determine true system

memory bus efficiency, the de-

signer must take into account

system/CPU overhead and the

randomness of the application.

Randomness can be defined as

the percentage of time that a

samebankaccessoccurs,which

isdependentontheapplication.

Adding more banks to the

DRAM hides the effects of ran-

domness, but it also increases

thecostoftheDRAM.Also,due

to the law of diminishing re-

turns, adding more banks will

not significantly improve per-

formance above a certain num-

ber.Basedoninputfromsystem

and DRAM designers on the

cost/performance trade-offs,

the industry seems to have

settled on 4-banks as the ideal

number. In Figure 4, both the

FCRAM and DDR devices used

in the calculations have four

banks.

One final note on Figure 4

is that the clock frequencies

used for FCRAM are higher

than for DDR. This is primarily

due to the DDR market cur-

rently using 100MHz/133MHz

as its mainstream products vs.

faster speeds being requested

by users of FCRAM (FCRAM

does have the capability to

achieve higher frequencies due

its simplified command struc-

ture and faster tRAC/tRC, which

result in better timing margin).

Regardless of the frequencies

used, FCRAM's improved bus

efficiency and resulting band-

width increases are clear.

In summary, the DRAM

marketisevolvingtooffermore

application-specific architec-

tures, which should be good

news for communication de-

signers. In particular, the

FCRAM is an architecture well-

suited for applications that re-

quire both low latency and high

bandwidth, such as high-per-

formance networking systems.

The FCRAM shines in these

types of applications, as it al-

lows the system designer to eas-

ily support DDR and FCRAM

with a common interface, yet

realizetheaddedbenefitsofthe

FCRAMintermsofasimplified

feature set, lower random cycle

latency and faster bus turn-

around times. The result is sig-

nificantly higher effective

bandwidth with minimal cost

increase.

[Communication Systems Design]





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