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LIN protocol keeps costs low for automotive nets

Posted: 16 Dec 2004     Print Version  Bookmark and Share

Keywords:LIN 

By Dan Butler

Principal Software Engineer

E-mail: dan.butler@

microchip.com

Thomas Schmidt

Sr. Applications Engineer

Automotive Products Group

E-mail: thomas.schmidt@

microchip.com

Thorsten Waclawczyk

Field Applications Engineer

E-mail: thorsten.waclawczyk@

microchip.com

Microchip Technology Inc.

Thelocalinterconnectnetwork

(LIN) protocol has been de-

signedbyaconsortiumofEuro-

peanvehiclemanufacturersasa

low-cost, short-distance, low-

speed network. It is intended to

communicatechangesinswitch

settings and respond to switch

changes,andthereforecommu-

nicates events that happen in

time scales of hundreds of mil-

liseconds,ratherthanthemuch

faster speeds associated with

other automotive applications,

such as engine management.

The protocol supports bidi-

rectional communication on a

single wire using inexpensive

microcontrollers driven by RC

oscillators to avoid the cost of

crystals or ceramic resonators.

Instead of paying the price in

accurate hardware, it pays the

price in time and software. An

autobaud step is included in ev-

ery message. Transfer rates of

up to 20Kbaud are supported,

along with a low-power sleep

mode, where the bus is shut

down to avoid draining the ve-

hicle battery. The bus can be

powered up by any node.

The bus is a cross between

I2

C and RS-232. It is pulled

high via a resistor, and each

node pulls it low via an open-

collector driver, such as I2

C.

Instead of having a clock line,

eachbyteismarkedbymeansof

start and stop bits; individual

bits are asynchronously timed

like RS-232.

Figure 1 shows a typical

LIN protocol configuration. A

dominant state is signalled by

a ground level on the bus and

occurs when any node pulls the

bus low. A recessive state oc-

curs when the bus is at the bat-

tery voltage, and occurs when

all nodes let the bus float. In

the idle state, the bus floats

high, pulled up through the

resistor.

The bus operates between

9Vand18V,butallcomponents

must survive 40V on the bus.

Typically, the microcontroller

is isolated from the bus by a line

driver/receiver. The bus is ter-

minated to Vbat at each node.

The master is terminated

through a 1k resistor, while

the slaves are terminated

through resistors between

20k and 47k. Maximum bus

length is designed to be 40m.

Each byte is framed by start

andstopbits.Thestartbitisthe

opposite of the idle state, or 0;

whilethestopbitequalstheidle

state(1).Withineachbyte,data

is transmitted starting with the

least significant bit (LSB).

Message protocol

The master controls the bus by

pollingslavestosharetheirdata

with the rest of the bus. Slave

nodes only transmit when com-

manded by the master, which

allows bidirectional communi-

cation without further arbitra-

tion. Message transfers start

with the master issuing a synch

break,followedbythesynchand

message fields. It also sets the

clockfortheentirebusbytrans-

mitting a synch field at the be-

ginning of each message.

Thesynchbreakisbusdomi-

nant, held for 13bit times, fol-

lowed by a stop bit (recessive).

This tells the slaves that a mes-

sage is coming. The master and

slaveclocksmayhavedriftedby

as much as 15 percent, so the

synch break may be received by

a slave as only 11bit times, or as

long as 15bit times.

Thesecondbyteofeachmes-

sage is an ident byte, which tells

thebuswhatdatawillfollowand

indicateswhichnodeshouldan-

swer and how long the answer

will be. Only one slave may re-

spond to a given command.

Slaves only transmit data on

the bus when directed by the

master. Once the data is on the

bus, any node may receive that

data. Therefore, communica-

tion from one slave to another

does not have to be directed

through the master.

As the protocol uses low-

cost RC oscillators, slaves must

detectthemaster'sbaudrateon

every transfer and adjust to the

current rate. For this reason,

each transaction starts with a

synch field, which is 1byte of

alternating 0s and 1s.

Error detection

The following errors must be

detected and counted within

each node. If there is an error,

thecommandshouldbeignored

and the error logged.

7 Bit errors--The transmitting

node should compare what it

LIN protocol keeps costs low

for automotive nets

thinks should be on the bus

againstwhatactuallyisonthe

bus. The controllers must

wait long enough for the bus

to respond before testing for

the bit. Given that the mini-

mum edge slew rate is 1V/5s

and that the maximum bus

voltage is 18V, the transmit-

ter should wait 185s before

testing.

7 Checksum errors--The data

content of each message is

protected by a checksum

byte, which is the inverted

module 256 checksum of the

data bytes.

7 Parity errors--The command

byte uses two parity bits to

protect the other six. These

need to be recalculated and

compared.

There is no direct error-re-

porting mechanism. As each

slave node is expected to track

its own errors, the master may

request error status as part of a

normal message protocol.

The LIN protocol is not di-

rectly compatible with the con-

trol area network (CAN) bus.

However, it is anticipated that

the two will operate in conjunc-

tion with one another. A CAN-

LIN protocol interface node

would be necessary to connect

the two buses, collecting infor-

mation from the LIN protocol

nodesandpassingittotheCAN

bus.

The master may direct all

nodes to enter a sleep mode by

Figure 1: A dominant state is signalled by a ground level on the bus while a recessive state occurs when the bus

is at the battery voltage. In the idle state, the bus floats high, pulled up through the resistor.

LIN

transceiver

Master

5C

Slave 1

5C

Slave 2

5C

Slave n < 16

5C

LIN

transceiver

LIN

transceiver

LIN

transceiver

40m

max.

VbatVbat Vbat Vbat

1k 30k nom. 30k nom. 30k nom.

LIN protocol

sending an ident code of 0x80.

The content of the data bytes

following the sleep command is

not defined. Slaves receiving

the sleep command should set

up for a wake-up on change

from the bus and power-down

to minimum current drain. The

bus will float high and not con-

sume current.

Any node may wake up the

bus by sending a signal. When

this is received, all nodes

should wake up and wait for the

master to start polling the bus

in the normal fashion.

Vbat

30k nom.

LIN protocol

Picmicro MCU

B1 B2 B5 B6 B7

B0

B4

LIN protocol

driver

Figure 2: Demonstration hardware consisting of two buttons and three

LEDs. LED1(2) changes state for every 10 pushes of button 1. In response

to ID1, the button counts are transmitted on the bus.

Figure 2 shows the demon-

stration hardware consisting of

two buttons and three LEDs.

LED1 changes state for every

10 pushes of button 1. Like-

wise, LED2 changes state for

every 10 pushes of button 2. In

response to ID1, the button

counts are transmitted on the

bus. In response to ID4, the

button counts are updated on

the bus.

Software operation

The LIN protocol works on the

interrupt as triggered from

RB0.Thisisnecessarytoimple-

ment the sleep/wake-up re-

quirement. Once the interrupt

istriggered,itcountsthelength

of the low-bit time. Then the

synch byte is read and the local

bit-time is determined. This is

then compared against the

originalbit-timetodetermineif

the original low-time was more

than 10bit-times, and thus sig-

nalled a synch break, or less

than 10, signalling a wake up

from sleep.

If it is a wake-up, the code

exits and continues waiting for

a synch break. If it is a synch

break, it then reads in the com-

mand byte, checks the parity

bits and checks the action table

to determine its actions from

there. The action table defines

thesourceordestinationforthe

data on the bus.

ToinitializetheLINprotocol

slave handler, the user calls the

routine InitLinSlave. This rou-

tine initializes the RB0 inter-

rupt pin and the TMR0. TMR0

will be used to measure the bit

length and to generate the baud

rate. After initialization, the

user can execute his code. The

code will be interrupted once a

falling edge is detected on RB0.

If it is detected, the code will

branch into the interrupt ser-

vice routine. All interrupts, ex-

cept for TMR0 and RB0, must

be disabled to allow the synch

field to be timed accurately. Af-

ter the baud rate is calculated,

the interrupt service routine is

exited.





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