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Nickname: asicwithankit     Articles(2)    Visits(39530)    Comments(5)    Votes(24)    RSS
ASIC with Ankit covers ASIC design verification, languages and methodology. The author, Ankit Gopani, works as a Lead Design Verification Engineer with SmartPlay Inc. He has 9 years of industry experience in ASIC design verification and executed several Verification projects.
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Posted: 01:09:30 PM, 27/05/2013
  Dear Readers,   Here I would like to share some understanding on keyword called "this". What is "this" in System Verilog? How does it used? Usage of "this" is simple but important in test bench development.   First of all......

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Posted: 12:52:59 AM, 19/05/2013
Dear Readers, System Verilog has new data type called ‘queue’ which can grow and shrink. With SV queue, we can easily add and remove elements anywhere that is the reason we say it can shrink and grow as we need. Queues can be used as LIFO (Last In First Out) Buffer or FIFO (First In F......

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