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Nickname: asicwithankit     Articles(7)    Visits(39535)    Comments(5)    Votes(24)    RSS
ASIC with Ankit covers ASIC design verification, languages and methodology. The author, Ankit Gopani, works as a Lead Design Verification Engineer with SmartPlay Inc. He has 9 years of industry experience in ASIC design verification and executed several Verification projects.
Blog Archive:
2015 -  Mar
2014 -  Nov
2013 -  May.,  Apr.,  Mar.,  Feb
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Posted: 07:19:19 AM, 09/11/2014
Dear Readers,   Mergers and acquisition are common in today’s global market. If you take a history of any successful big companies in the market for more than 10-15 year, you would see the list of companies they acquired. So now two questions comes in mind. "Companies does a......

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Posted: 01:56:26 AM, 08/02/2013
As we all know the semiconductor market looks good now days and lots of companies are hiring talents for 2013-14 projection. If we keep this projection in mind, we could say there would be a business for the companies for upcoming years. Now, the billion dollar question: ‘how about the resou......

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Posted: 06:23:54 AM, 16/03/2015
We have been implementing every possible checks to make sure design is verified but what have we done to check our test bench ? How do we make sure that our test bench has covered everything that needs to be covered w.r.t to specification and test plans ? Here is the place “Functional Covera......

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Posted: 01:09:30 PM, 27/05/2013
  Dear Readers,   Here I would like to share some understanding on keyword called "this". What is "this" in System Verilog? How does it used? Usage of "this" is simple but important in test bench development.   First of all......

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Posted: 12:52:59 AM, 19/05/2013
Dear Readers, System Verilog has new data type called ‘queue’ which can grow and shrink. With SV queue, we can easily add and remove elements anywhere that is the reason we say it can shrink and grow as we need. Queues can be used as LIFO (Last In First Out) Buffer or FIFO (First In F......

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Posted: 01:03:50 PM, 29/04/2013
Dear Readers, We have been using standard languages and methodologies for ASIC/FPGA design and Verification activities. We as an engineer must know on history of verification activities. Today we mostly work on verification standard languages like System Verilog. The whole industry is moving to a......

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Posted: 09:53:54 PM, 13/03/2013
Dear Readers, I have been hearing on re-spins of chips. Many companies have gone through this painful phase because of several reason/defects. Nobody likes re-spin for chip as it is expensive and time consuming! Companies have a fear to loose time to market for their products because of this reas......

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